Synchronous two PWM signals generator

Stas I. (stasik_30) OP 2021-07-22 13:46 #6765552

Rate this post

•	▲ useful ▼ not useful

Hi to all,

I try to generate two synchronous PWM signals however I missing 
something. I'll be grateful if you could assist me.

1. Two signals should start at the same time.

2. When PWM_1 is rising edge the PWM_2 should be start either.

3. PWM_1 is 1us period , 0.5 uS high ('1') and 0.5 uS low ('0'). 50% 
Duty cycle.

4. PWM_2 is 1uS period , 0.3uS high ('1') and 0.7 us low ('0'). 30% Duty 
cycle.

Code and simulation attached .

Simulation :
Attached image of simulation Sim.PNG




CODE :

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY clk1 IS
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_out : OUT STD_LOGIC;
pwm_1 : OUT STD_LOGIC;
pwm_2 : OUT STD_LOGIC
END clk1;
ARCHITECTURE Behavioral OF clk1 IS
SIGNAL temporal_1 : STD_LOGIC;
SIGNAL temporal_2 : STD_LOGIC;
SIGNAL temporal_4 : STD_LOGIC;
SIGNAL counter_1 : INTEGER RANGE 0 TO 4 := 0;--780 original
SIGNAL counter_2 : INTEGER RANGE 0 TO 4 := 0;--780 original
SIGNAL counter_3 : INTEGER RANGE 0 TO 4 := 0;--780 original
SIGNAL counter_4 : INTEGER RANGE 0 TO 4 := 0;--780 original
freq_divider_1 : PROCESS (reset, clk)
IF rising_edge(clk) THEN
counter_3 <=counter_3+1;
--counter_4 <=counter_3+1;
IF (reset = '1') THEN
temporal_1 <= '0';
counter_1 <= 0;
ELSIF rising_edge(clk) THEN
IF (counter_1 = 4) THEN
temporal_1 <= NOT(temporal_1);
counter_1 <= 0;
counter_1 <= counter_1 + 1;
IF (reset = '1') THEN
temporal_2 <= '0';
counter_2 <= 0;
ELSIF rising_edge(clk) THEN
IF (counter_2 = 3) THEN
temporal_2 <= NOT(temporal_2);
counter_2 <= 0;
counter_2 <= counter_2 + 1;
IF counter_2 = 2 THEN
temporal_2 <= '0';
temporal_2 <=temporal_2;
END PROCESS;
clk_out <= temporal_1;
pwm_1 <= temporal_1;
pwm_2 <= temporal_2;
END Behavioral;




Thanks.

Stas.

Attached files:

Sim.PNG (19 KB)

Reply Quote Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Report post

Lothar M. (lkmiller) Moderator (Company: Titel) 2021-07-22 14:58 #6765644

Rate this post

•	▲ useful ▼ not useful

The forum sw has some problems with correct rendering since the last 
update...

But to cut down your code it looks like that:

freq_divider_1 : PROCESS (reset, clk)
IF rising_edge(clk) THEN
IF (reset = '1') THEN
ELSIF rising_edge(clk) THEN
IF (reset = '1') THEN
ELSIF rising_edge(clk) THEN
END PROCESS;

Where did you find that fairless amazing coding style with several 
"subprocesses" in one process?

Are you sure, that your synthesizer is able to generate hardware out of 
this?

> however I missing something.
I would implement 1 counter steadily counting from 0 to 9. One step each 
100ns. Then I would set both of the PWM outputs high with counter = 0, 
and I would reset one PWM output with counter = 4 and the second PWM 
output with counter = 6. Sounds kind of easy...

Reply Quote Edit Delete Report post

Stas I. (stasik_30) OP 2021-07-27 13:55 #6771032

Rate this post

•	▲ useful ▼ not useful

Thank you Lothar.
It has been synthesized. I tried what you had offered and the  PWM 2 
doesn't starts synchronous with PWM 1, it synchronous for the first time 
only.

I changed my code at all. Similar to state machine.
Thank you a lot.
My regards,
Stas.

Reply Quote Edit Delete Report post

Lothar M. (lkmiller) Moderator (Company: Titel) 2021-07-27 14:36 #6771076

Rate this post

•	▲ useful ▼ not useful

Stas I. wrote:
> I tried what you had offered and the  PWM 2 doesn't starts synchronous
> with PWM 1, it synchronous for the first time only.
With only 1 counter for both of those PWM outputs they never ever can 
get out of synchronicity:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity doublepwm is
    Port ( clk  : in  STD_LOGIC;
           pwm1 : out  STD_LOGIC := '1';
           pwm2 : out  STD_LOGIC := '1');
end doublepwm;
architecture Behavioral of doublepwm is
signal cnt : integer range 0 to 9 := 0;
constant pwmvalue_1 : integer := 5;
constant pwmvalue_2 : integer := 3;
   process begin
      wait until rising_edge(clk);
      if cnt = 9 then  cnt <= 0;
      else             cnt <= cnt + 1;
      end if;
      if cnt = 0 then
         pwm1 <= '1';
         pwm2 <= '1';
      end if;
      if cnt = pwmvalue_1 then
         pwm1 <= '0';
      end if;
      if cnt = pwmvalue_2 then
         pwm2 <= '0';
      end if;
   end process;
end Behavioral;

Attached files:

doublepwm_wf.PNG (8.7 KB)

Reply Quote Edit Delete Report post