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Synchronous two PWM signals generator
von Stas I. (stasik_30)

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Hi to all,

I try to generate two synchronous PWM signals however I missing 
something. I'll be grateful if you could assist me.

1. Two signals should start at the same time.

2. When PWM_1 is rising edge the PWM_2 should be start either.

3. PWM_1 is 1us period , 0.5 uS high ('1') and 0.5 uS low ('0'). 50% 
Duty cycle.

4. PWM_2 is 1uS period , 0.3uS high ('1') and 0.7 us low ('0'). 30% Duty 
cycle.

Code and simulation attached .

Simulation :
Attached image of simulation Sim.PNG




CODE :
1
LIBRARY IEEE;

2
USE IEEE.STD_LOGIC_1164.ALL;

3
4
ENTITY clk1 IS

5
PORT (

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clk : IN STD_LOGIC;

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reset : IN STD_LOGIC;

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clk_out : OUT STD_LOGIC;

9
pwm_1 : OUT STD_LOGIC;

10
pwm_2 : OUT STD_LOGIC

11
);

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END clk1;

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14
ARCHITECTURE Behavioral OF clk1 IS

15
SIGNAL temporal_1 : STD_LOGIC;

16
SIGNAL temporal_2 : STD_LOGIC;

17
SIGNAL temporal_4 : STD_LOGIC;

18
SIGNAL counter_1 : INTEGER RANGE 0 TO 4 := 0;--780 original

19
SIGNAL counter_2 : INTEGER RANGE 0 TO 4 := 0;--780 original

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SIGNAL counter_3 : INTEGER RANGE 0 TO 4 := 0;--780 original

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SIGNAL counter_4 : INTEGER RANGE 0 TO 4 := 0;--780 original

22
BEGIN

23
freq_divider_1 : PROCESS (reset, clk)

24
BEGIN

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IF rising_edge(clk) THEN

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counter_3 <=counter_3+1;

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--counter_4 <=counter_3+1;

29
END IF;

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IF (reset = '1') THEN

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temporal_1 <= '0';

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counter_1 <= 0;

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ELSIF rising_edge(clk) THEN

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IF (counter_1 = 4) THEN

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temporal_1 <= NOT(temporal_1);

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counter_1 <= 0;

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ELSE

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counter_1 <= counter_1 + 1;

43
END IF;

44
45
END IF;

46
47
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IF (reset = '1') THEN

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temporal_2 <= '0';

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counter_2 <= 0;

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ELSIF rising_edge(clk) THEN

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IF (counter_2 = 3) THEN

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temporal_2 <= NOT(temporal_2);

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counter_2 <= 0;

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ELSE

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counter_2 <= counter_2 + 1;

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IF counter_2 = 2 THEN

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temporal_2 <= '0';

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ELSE

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temporal_2 <=temporal_2;

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END IF;

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END IF;

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END IF;

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END PROCESS;

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clk_out <= temporal_1;

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pwm_1 <= temporal_1;

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pwm_2 <= temporal_2;

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END Behavioral;




Thanks.

Stas.

  


  



  

  
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    Re: Synchronous two PWM signals generator
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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The forum sw has some problems with correct rendering since the last 
update...

But to cut down your code it looks like that:
1
freq_divider_1 : PROCESS (reset, clk)

2
BEGIN

3
4
IF rising_edge(clk) THEN

5
:

6
END IF;

7
8
9
IF (reset = '1') THEN

10
:

11
ELSIF rising_edge(clk) THEN

12
:

13
END IF;

14
15
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IF (reset = '1') THEN

17
:

18
ELSIF rising_edge(clk) THEN

19
:

20
END IF;

21
22
END PROCESS;

Where did you find that fairless amazing coding style with several 
"subprocesses" in one process?

Are you sure, that your synthesizer is able to generate hardware out of 
this?

> however I missing something.
I would implement 1 counter steadily counting from 0 to 9. One step each 
100ns. Then I would set both of the PWM outputs high with counter = 0, 
and I would reset one PWM output with counter = 4 and the second PWM 
output with counter = 6. Sounds kind of easy...

  


  




  

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    Re: Synchronous two PWM signals generator
  


  

    

      von
      
        Stas I.
        (stasik_30)
        
      
      


      
    


    

      
    

    

    

  
  


  

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Thank you Lothar.
It has been synthesized. I tried what you had offered and the  PWM 2 
doesn't starts synchronous with PWM 1, it synchronous for the first time 
only.

I changed my code at all. Similar to state machine.
Thank you a lot.
My regards,
Stas.

  


  




  

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    Re: Synchronous two PWM signals generator
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

      

      

      Attached files:



        
    

  
  


  

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Stas I. wrote:
> I tried what you had offered and the  PWM 2 doesn't starts synchronous
> with PWM 1, it synchronous for the first time only.
With only 1 counter for both of those PWM outputs they never ever can 
get out of synchronicity:
1
library IEEE;

2
use IEEE.STD_LOGIC_1164.ALL;

3
4
use IEEE.NUMERIC_STD.ALL;

5
6
entity doublepwm is

7
    Port ( clk  : in  STD_LOGIC;

8
           pwm1 : out  STD_LOGIC := '1';

9
           pwm2 : out  STD_LOGIC := '1');

10
end doublepwm;

11
12
architecture Behavioral of doublepwm is

13
signal cnt : integer range 0 to 9 := 0;

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constant pwmvalue_1 : integer := 5;

15
constant pwmvalue_2 : integer := 3;

16
begin

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   process begin

18
      wait until rising_edge(clk);

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      if cnt = 9 then  cnt <= 0;

21
      else             cnt <= cnt + 1;

22
      end if;

23
      

24
      if cnt = 0 then

25
         pwm1 <= '1';

26
         pwm2 <= '1';

27
      end if;

28
      

29
      if cnt = pwmvalue_1 then

30
         pwm1 <= '0';

31
      end if;

32
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      if cnt = pwmvalue_2 then

34
         pwm2 <= '0';

35
      end if;

36
      

37
   end process;

38
end Behavioral;


  


  




  

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