Guest
#6757146
Hello everybody, I'm studying the primitives in verilog and I don't really see any use for them. I explain: Imagine you want to describe an AND gate, what would you do? a) assign OUT = A & B; b) and (OUT, A, B); So what is the true power of primitives? Why do they exist? I have seen that users can create our own primitives (UDP), but the reasoning I have is the same: Why use this option of the verilog if we can describe our circuit with a "module"? Thanks