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Forum: FPGA, VHDL & Verilog I need to clarify a question about verilog


von Black (Guest)


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Hello everybody,

I'm studying the primitives in verilog and I don't really see any use 
for them. I explain:

Imagine you want to describe an AND gate, what would you do?

a) assign OUT = A & B;

b) and (OUT, A, B);

So what is the true power of primitives? Why do they exist?

I have seen that users can create our own primitives (UDP), but the 
reasoning I have is the same: Why use this option of the verilog if we 
can describe our circuit with a "module"?

Thanks

von black is the color of ash (Guest)


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Black wrote:
> Why use this option of the verilog if we
> can describe our circuit with a "module"?

Depends if you wanna do behavioral or gate level/Netlist simulation. And 
how good (or brain dead) your synthesize tool is. See Gajski-diagram:

https://www.researchgate.net/figure/Gajski-and-Kuhns-Y-Chart-1982_fig2_283142112

von Black (Guest)


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But, if we have:

a) assign OUT = A & B;

b) and (OUT, A, B);

both are gate-level descriptions, aren't they?

von black is the color of ash (Guest)


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Black wrote:
> a) assign OUT = A & B;
>
> b) and (OUT, A, B);
>
> both are gate-level descriptions, aren't they?


a) looks more behavioral, it could be iplemented with a mux-module also; 
i.e.

mux(OUT (OUT), .sel (a), IN1 ('0'), IN2 (B))
and therefore with a different gate

von Black (Guest)


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I think I understand your explanation, so if I want to implement an AND 
gate in an FPGA it is absurd to use primitives right? Because FPGAs are 
going to use their Logic Blocks for it.

Then, the use of primitives is done in the description of ASICs, right?

von FPGA_Notfallseelsorge (Guest)


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As i understand it, primitives can be defined for much more complex 
descriptions. It makes no sense for a simple gate, but this is a very 
simple primitive.

With complexer primitives it will save you writing efford as you just 
have to use the primitive.

For an FPGA it will somehow be mapped to ressorces available in the 
FPGA. For an ASIC it will be mapped to structure components in some Cell 
library.

von FPGAküchle (Guest)


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What is the purpose of C-Code? - to be translated by a compiler from a 
high level description into executable binary code

What ist the purpose of a verilog description? -
A) to VERIfy LOGic, regardless if given as a netlist of circuitry or 
logic-equation
AND ALSO
B) to be translated from a (more or less) abstract description into a 
netlist
describing (real) circuitry.

The purpose (A)-Simulation of handwritten or generated netlist (with 
back propagation) was the first when verilog was 'invented', verilog was 
intended to be run in a simulator only.

The purpose (B) -Synthesize were later add to the 'use-case' of 
verilog-coded hardware descriptions.

It seems, that purpose (A) is mostly forgot by today's user, they are 
confused with the use of computer programming language as C.

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