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Forum: FPGA, VHDL & Verilog Compile warnings in model sim


Compile warnings in model sim
von Peter Reitinger (Guest)

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Hello, I get compile warnings (and later compile errors from other 
parts, but one after another...) in model sim with the following code.
I do not get compile warnings when synthesizing the code with Lattice 
Diamond nor when compiling it with Active HDL.

What is wrong with the following code?

1
type TPhOptions is record

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sigPrintheadKCE      : std_logic;

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sigPH_PICAIIRohm    : std_logic;

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sigReg_Chan_Offs_6    : std_logic_vector( 7 downto 0);   sigReg_Chan_Offs_5    : std_logic_vector( 7 downto 0);   sigReg_Chan_Offs_4    : std_logic_vector( 7 downto 0);   sigReg_Chan_Offs_3    : std_logic_vector( 7 downto 0);   sigReg_Chan_Offs_2    : std_logic_vector( 7 downto 0);   sigReg_Chan_Offs_1    : std_logic_vector( 7 downto 0); 

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sigReg_Words_Per_Ch    : std_logic_vector( 7 downto 0);

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sigReg_LineOffs      : std_logic_vector( 7 downto 0);

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sigSPI_Clk_Duration    : std_logic_vector( 3 downto 0);

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sigSPI_Clk_Duty      : std_logic_vector( 3 downto 0);

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sigSPI_DataSwitch    : std_logic_vector( 3 downto 0);

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Bit16perLine      : std_logic_vector( 7 downto 0);

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sigEnableChannel      : std_logic_vector( 5 downto 0);

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REG_Latch_Setup_Time  : std_logic_vector( 7 downto 0);

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REG_Latch_End_Time    : std_logic_vector( 7 downto 0);

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REG_Strobe_Setup_Time  : std_logic_vector( 7 downto 0);

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REG_Burn_Prescaler    : std_logic_vector( 7 downto 0);

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sigReg_HeadFill32    : std_logic_vector( 7 downto 0);

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end record;

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-- then usage of length attribute in following constant definition

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  constant PH_OPTIONS_LEN: integer := 

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    1 + 

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    1 + 

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    work.fpga_configP_helper.TPhOptions.sigReg_Chan_Offs_6'length +

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    TPhOptions.sigReg_Chan_Offs_5'length +

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    TPhOptions.sigReg_Chan_Offs_4'length +

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    TPhOptions.sigReg_Chan_Offs_3'length +

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    TPhOptions.sigReg_Chan_Offs_2'length +

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    TPhOptions.sigReg_Chan_Offs_1'length +

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    TPhOptions.sigReg_Words_Per_Ch'length +

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    TPhOptions.sigReg_LineOffs'length +

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    TPhOptions.sigSPI_Clk_Duration'length +

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    TPhOptions.sigSPI_Clk_Duty'length +

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    TPhOptions.sigSPI_DataSwitch'length +

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    TPhOptions.Bit16perLine'length +

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    TPhOptions.sigEnableChannel'length +

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    TPhOptions.REG_Latch_Setup_Time'length +

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    TPhOptions.REG_Latch_End_Time'length +

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    TPhOptions.REG_Strobe_Setup_Time'length +

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    TPhOptions.REG_Burn_Prescaler'length +

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    TPhOptions.sigReg_HeadFill32'length

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  ;

1
-- warnings:

2
# ** Warning: E:/SAUBER/lfe5um25_octavo/impl1/source/fpga_configP.vhd(38): (vcom-1260) Type mark (TPhOptions) cannot be prefix of selected name.

3
# ** Warning: E:/SAUBER/lfe5um25_octavo/impl1/source/fpga_configP.vhd(39): (vcom-1260) Type mark (TPhOptions) cannot be prefix of selected name.

4
# ** Warning: E:/SAUBER/lfe5um25_octavo/impl1/source/fpga_configP.vhd(40): (vcom-1260) Type mark (TPhOptions) cannot be prefix of selected name.

5
# ** Warning: E:/SAUBER/lfe5um25_octavo/impl1/source/fpga_configP.vhd(41): (vcom-1260) Type mark (TPhOptions) cannot be prefix of selected name.

6
# ** Warning: E:/SAUBER/lfe5um25_octavo/impl1/source/fpga_configP.vhd(42): (vcom-1260) Type mark (TPhOptions) cannot be prefix of selected name.

7
# ** Warning: E:/SAUBER/lfe5um25_octavo/impl1/source/fpga_configP.vhd(43): (vcom-1260) Type mark (TPhOptions) cannot be prefix of selected name.

8
# ** Warning: E:/SAUBER/lfe5um25_octavo/impl1/source/fpga_configP.vhd(44): (vcom-1260) Type mark (TPhOptions) cannot be prefix of selected name.

9
# ** Warning: E:/SAUBER/lfe5um25_octavo/impl1/source/fpga_configP.vhd(45): (vcom-1260) Type mark (TPhOptions) cannot be prefix of selected name.

10
# ** Warning: E:/SAUBER/lfe5um25_octavo/impl1/source/fpga_configP.vhd(46): (vcom-1260) Type mark (TPhOptions) cannot be prefix of selected name.

11
# ** Warning: E:/SAUBER/lfe5um25_octavo/impl1/source/fpga_configP.vhd(47): (vcom-1260) Type mark (TPhOptions) cannot be prefix of selected name.

12
# ** Warning: E:/SAUBER/lfe5um25_octavo/impl1/source/fpga_configP.vhd(48): (vcom-1260) Type mark (TPhOptions) cannot be prefix of selected name.

13
# ** Warning: E:/SAUBER/lfe5um25_octavo/impl1/source/fpga_configP.vhd(49): (vcom-1260) Type mark (TPhOptions) cannot be prefix of selected name.

14
# ** Warning: E:/SAUBER/lfe5um25_octavo/impl1/source/fpga_configP.vhd(51): (vcom-1260) Type mark (TPhOptions) cannot be prefix of selected name.

15
# ** Warning: E:/SAUBER/lfe5um25_octavo/impl1/source/fpga_configP.vhd(52): (vcom-1260) Type mark (TPhOptions) cannot be prefix of selected name.

16
# ** Warning: E:/SAUBER/lfe5um25_octavo/impl1/source/fpga_configP.vhd(53): (vcom-1260) Type mark (TPhOptions) cannot be prefix of selected name.

17
# ** Warning: E:/SAUBER/lfe5um25_octavo/impl1/source/fpga_configP.vhd(54): (vcom-1260) Type mark (TPhOptions) cannot be prefix of selected name.

18
# ** Warning: E:/SAUBER/lfe5um25_octavo/impl1/source/fpga_configP.vhd(55): (vcom-1260) Type mark (TPhOptions) cannot be prefix of selected name.

19
# ** Warning: E:/SAUBER/lfe5um25_octavo/impl1/source/fpga_configP.vhd(56): (vcom-1260) Type mark (TPhOptions) cannot be prefix of selected name.


  


  




  

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    Re: Compile warnings in model sim
  


  

    

      von
      
        -gb- (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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And this is how it works:

1
library IEEE;

2
use IEEE.STD_LOGIC_1164.ALL;

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use IEEE.NUMERIC_STD.ALL;

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entity test_record is

6
end test_record;

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architecture tb of test_record is

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type TPhOptions is record

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  sigPrintheadKCE       : std_logic;

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  sigPH_PICAIIRohm      : std_logic;

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  sigReg_Chan_Offs_6    : std_logic_vector( 7 downto 0);

14
  sigReg_Chan_Offs_5    : std_logic_vector( 7 downto 0);

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  sigReg_Chan_Offs_4    : std_logic_vector( 7 downto 0);

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  sigReg_Chan_Offs_3    : std_logic_vector( 7 downto 0);

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  sigReg_Chan_Offs_2    : std_logic_vector( 7 downto 0);

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  sigReg_Chan_Offs_1    : std_logic_vector( 7 downto 0);

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  sigReg_Words_Per_Ch   : std_logic_vector( 7 downto 0);

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  sigReg_LineOffs       : std_logic_vector( 7 downto 0);

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  sigSPI_Clk_Duration   : std_logic_vector( 3 downto 0);

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  sigSPI_Clk_Duty       : std_logic_vector( 3 downto 0);

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  sigSPI_DataSwitch     : std_logic_vector( 3 downto 0);

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  Bit16perLine          : std_logic_vector( 7 downto 0);

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  sigEnableChannel      : std_logic_vector( 5 downto 0);

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  REG_Latch_Setup_Time  : std_logic_vector( 7 downto 0);

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  REG_Latch_End_Time    : std_logic_vector( 7 downto 0);

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  REG_Strobe_Setup_Time : std_logic_vector( 7 downto 0);

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  REG_Burn_Prescaler    : std_logic_vector( 7 downto 0);

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  sigReg_HeadFill32     : std_logic_vector( 7 downto 0);

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end record;

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signal REC : TPhOptions;

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constant REC_LEN : integer := 

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  1 + 

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  1 + 

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  REC.sigReg_Chan_Offs_6'length +

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  REC.sigReg_Chan_Offs_5'length +

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  REC.sigReg_Chan_Offs_4'length +

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  REC.sigReg_Chan_Offs_3'length +

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  REC.sigReg_Chan_Offs_2'length +

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  REC.sigReg_Chan_Offs_1'length +

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  REC.sigReg_Words_Per_Ch'length +

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  REC.sigReg_LineOffs'length +

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  REC.sigSPI_Clk_Duration'length +

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  REC.sigSPI_Clk_Duty'length +

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  REC.sigSPI_DataSwitch'length +

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  REC.Bit16perLine'length +

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  REC.sigEnableChannel'length +

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  REC.REG_Latch_Setup_Time'length +

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  REC.REG_Latch_End_Time'length +

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  REC.REG_Strobe_Setup_Time'length +

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  REC.REG_Burn_Prescaler'length +

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  REC.sigReg_HeadFill32'length;

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begin

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process begin

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  wait for 10 ns;

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  report "REC_LEN: " & integer'image(REC_LEN);

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  wait;

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end process;

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end;


Alles Gute alles Liebe (-:

  


  




  

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    Re: Compile warnings in model sim
  


  

    

      von
      
        -gb- (Guest)
      
      


      
    


    

      
    

    

    

      

      

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Sorry for the formatting, this is done by the Forumsoftware and just 
awful (in school i learned awefull). So here is the code as .vhd file 
too.

  


  




  

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    Re: Compile warnings in model sim
  


  

    

      von
      
        -gb- (Guest)
      
      


      
    


    

      
    

    

    

      

      

      Attached files:



        
    

  
  


  

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Wahhhh!!!! the "highlighted code" function just renders as bad as inline 
code. don't click that!
The image shows how the code is supposed to look - and did before the 
forumsoftware was "schlimmbessered".

  


  




  

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    Re: Compile warnings in model sim
  


  

    

      von
      
        Gustl B.
        (-gb-)
        
      
      


      
    


    

      
    

    

    

  
  


  

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-gb- wrote:
> "schlimmbessered"

This is the german word for "trying with best intentions, but failing in 
an so absurd way, that the outcome is even worse than the starting 
condition."

  


  




  

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