Hello Guys
I got a Problem. I made a shift register who is counting from 0 to 12
over and over and Some Outputs.
It looks like this:
1  entity Ampel is

2  Port ( ROT : out STD_LOGIC;

3  GRÜN : out STD_LOGIC;

4  GELB : out STD_LOGIC;

5  cnt : inout integer range 0 to 12:=0;

6  clk : in STD_LOGIC);

7  end Ampel;

8  
9  architecture Behavioral of Ampel is

10  
11  begin

12  process (clk)

13  begin

14  
15  if rising_edge (clk) then

16  if cnt=12 then cnt <= 0

17  else

18  cnt <= cnt + 1;

19  end if;

20  end if;

21  end process;

22  
23  
24  
25  
26  end Behavioral;

If cnt = 0  4 ROT should be 1
if cnt = 5 GELB and ROT should be 1 and so on..
could anyone migth help me with this Problem ?