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Forum: FPGA, VHDL & Verilog get some outputsignals if cnt reaches an exact amount


get some outputsignals if cnt reaches an exact amount
von Steven Tumler (Guest)

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Hello Guys

I got a Problem. I made a shift register who is counting from 0 to 12 
over and over and Some Outputs.

It looks like this:
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entity Ampel is

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    Port ( ROT : out  STD_LOGIC;

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           GRÜN : out  STD_LOGIC;

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           GELB : out  STD_LOGIC;

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           cnt : inout integer range 0 to 12:=0;

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           clk : in  STD_LOGIC);

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end Ampel;

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architecture Behavioral of Ampel is

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begin

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process (clk)

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begin

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if rising_edge (clk) then

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  if cnt=12 then cnt <= 0

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   else          

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   cnt <= cnt + 1;

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    end if;

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  end if;

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end process;

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end Behavioral;



If cnt = 0 - 4 ROT should be 1
if cnt = 5 GELB and ROT should be 1 and so on..

could anyone migth help me with this Problem ?

  


  



  

  
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ROT <= '1' when cnt < 5 else '0';


Steven Tumler wrote:
> if cnt = 5 GELB and ROT should be 1 and so on..

Too unspecific.

Steven Tumler wrote:
> GRÜN

Contains "Ü" which may cause Problems.

Use the [vhdl] Tags for VHDL Code.

  


  




  

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    Re: get some outputsignals if cnt reaches an exact amount
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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Steven Tumler wrote:
> cnt : inout integer range 0 to 12:=0;
Where the heck did you find this lazy coding style?
Is it your own way of reducing lines of code?

Short: never ever use a port as a signal. You will encounter strange 
problems in simulation later on.

> could anyone migth help me with this Problem ?
 What problems do you encounter? What do you want to happen? And what 
else happens instead? What error messages are reported by which 
toolchain?

> I made a shift register who is counting
You could use the German FPGA forum of µc.net if thats more convenient 
for you:
https://www.mikrocontroller.net/forum/fpga-vhdl-cpld

  


  




  

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