EmbDev.net

Forum: FPGA, VHDL & Verilog How to implement lookup table in VHDL


von Were to lookup? (Guest)


Rate this post
useful
not useful
What is the fastest / most efficient way to generate a lookup table in 
VHDL? I have a nonlinear function which I would like to implement and my 
data is currently available as an array in Matlab. For the lookup table 
I intended to us a simple case statement but that implies that I had to 
manually code all the different cases in the VHDL editor, i.e. filling 
in the data of the table manually into the source file.

Is there a proper way how this is done? The only way I see so far would 
be, to write a MATLAB script which prints the VHDL code based on my data 
array into a file. This would probably work but seems to be reinventing 
the wheel since I'm for sure not the first one who has to generate a 
lookup table in VHDL. So what's the correct solution for such a task?

: Moved by Moderator
von Achim S. (Guest)


Rate this post
useful
not useful
wouldn't it be an option to use a RAM-structure (e.g. a BRAM) als 
lookup-table? And your Matlab-script just provides an 
initialization-file for the RAM.

von Christoph Z. (christophz)


Rate this post
useful
not useful
Were to lookup? schrieb:
> Is there a proper way how this is done? The only way I see so far would
> be, to write a MATLAB script which prints the VHDL code based on my data
> array into a file. This would probably work but seems to be reinventing
> the wheel since I'm for sure not the first one who has to generate a
> lookup table in VHDL.

Your idea to generate VHDL from Matlab is quite common and I would say 
it is also quite efficient. (You can even throw money at Mathworks and 
get toolboxes that do that for you).

Instead of generating a huge switch case statement I would actually 
export it as table. Define a two dimensional type that fits your table 
data (define that type as well if it makes live easier). Then export 
your table as a constant with initialization.
All of this goes into a VHDL package, which makes it possible to include 
it in other files of your VHDL design. This is important to separate 
manually written and generated files.

: Edited by User
von Jürgen S. (engineer)


Rate this post
useful
not useful
I'd prefer a MIF to be generated. The Synthesis can move this to a 
LUT-only implementation at any point of time. At least if you disallow 
BRAM usage.

von Where to lookup? (Guest)


Rate this post
useful
not useful
Thanks for all the inputs.

Christoph Z. schrieb:
> Your idea to generate VHDL from Matlab is quite common and I would say
> it is also quite efficient. (You can even throw money at Mathworks and
> get toolboxes that do that for you).
This is how I solved it now since it seemed at least not to be the most 
stupid solution.

Jürgen S. schrieb:
> I'd prefer a MIF to be generated. The Synthesis can move this to a
> LUT-only implementation at any point of time. At least if you disallow
> BRAM usage.

What is a MIF? Google suggested "memory configuration file", I guess 
that is what you referred to?

I will definitely have an eye on the other possibilities too once I find 
the time to do so.

von Vancouver (Guest)


Rate this post
useful
not useful
Unfortunately, you gave too less information to answer this question 
precisely. Are you planning only simulation with the VHDL model? Are you 
targeting FPGA? Which FPGA? Are you planning ASIC implementation? Shall 
the code be technology independent?

For Xilinx FPGA, it may be a good idea to generate a block ROM macro, as 
described in the Xilinx Vivado Design User Guide (UG901), Section "ROM 
HDL coding Techniques". Since it is all HDL code, you can generate is 
completely from MatLab. But this is only one possible solution. It does 
not work for ASIC and for simulation-only models there are easier ways 
to go.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig