What is the fastest / most efficient way to generate a lookup table in VHDL? I have a nonlinear function which I would like to implement and my data is currently available as an array in Matlab. For the lookup table I intended to us a simple case statement but that implies that I had to manually code all the different cases in the VHDL editor, i.e. filling in the data of the table manually into the source file. Is there a proper way how this is done? The only way I see so far would be, to write a MATLAB script which prints the VHDL code based on my data array into a file. This would probably work but seems to be reinventing the wheel since I'm for sure not the first one who has to generate a lookup table in VHDL. So what's the correct solution for such a task?
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wouldn't it be an option to use a RAM-structure (e.g. a BRAM) als lookup-table? And your Matlab-script just provides an initialization-file for the RAM.
Were to lookup? schrieb: > Is there a proper way how this is done? The only way I see so far would > be, to write a MATLAB script which prints the VHDL code based on my data > array into a file. This would probably work but seems to be reinventing > the wheel since I'm for sure not the first one who has to generate a > lookup table in VHDL. Your idea to generate VHDL from Matlab is quite common and I would say it is also quite efficient. (You can even throw money at Mathworks and get toolboxes that do that for you). Instead of generating a huge switch case statement I would actually export it as table. Define a two dimensional type that fits your table data (define that type as well if it makes live easier). Then export your table as a constant with initialization. All of this goes into a VHDL package, which makes it possible to include it in other files of your VHDL design. This is important to separate manually written and generated files.
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I'd prefer a MIF to be generated. The Synthesis can move this to a LUT-only implementation at any point of time. At least if you disallow BRAM usage.
Thanks for all the inputs. Christoph Z. schrieb: > Your idea to generate VHDL from Matlab is quite common and I would say > it is also quite efficient. (You can even throw money at Mathworks and > get toolboxes that do that for you). This is how I solved it now since it seemed at least not to be the most stupid solution. Jürgen S. schrieb: > I'd prefer a MIF to be generated. The Synthesis can move this to a > LUT-only implementation at any point of time. At least if you disallow > BRAM usage. What is a MIF? Google suggested "memory configuration file", I guess that is what you referred to? I will definitely have an eye on the other possibilities too once I find the time to do so.
Unfortunately, you gave too less information to answer this question precisely. Are you planning only simulation with the VHDL model? Are you targeting FPGA? Which FPGA? Are you planning ASIC implementation? Shall the code be technology independent? For Xilinx FPGA, it may be a good idea to generate a block ROM macro, as described in the Xilinx Vivado Design User Guide (UG901), Section "ROM HDL coding Techniques". Since it is all HDL code, you can generate is completely from MatLab. But this is only one possible solution. It does not work for ASIC and for simulation-only models there are easier ways to go.
This article could be beneficial for you, its also discusses glitch issues in LUT https://hardwarebee.com/overview-of-lookup-tables-in-fpga-design/
Achim S. wrote: > wouldn't it be an option to use a RAM-structure (e.g. a BRAM) als > lookup-table? Every LUT in an FPGA IS RAM. Take a 6-Input Lut. It stores 2^6 Bits Memory, has 6 Address Inputs and 1 Data Output. So BRAM is ofcourse a good way to implement larger LUTs with wider Datawidth and deeper Depth. Just store the values in the right order inside the BRAM.