counter with signal enable (active high) and synchronous reset signal (active high)

Juan Guest 2020-12-27 20:32 #6526988

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I'm trying to do the following task, but I need your help or some 
pointers:

Write a counter with signal enable (active high) and synchronous reset 
signal (active high) to a VHDL file (cont_clk.vhd).
The counter should generate an end of count (rco) output signal that 
turns high every 1 millisecond and which is active for one clock cycle 
(clk). It should also generate a count signal (q) of 14 bits.

Use the counter scheme (sequential circuit) described below.

The module should have the following entity declaration:

entity cont_clk is
 Port (enable: in STD_LOGIC;
 reset: in STD_LOGIC;
 clk: in STD_LOGIC;
 rco: out STD_LOGIC;
 q: out STD_LOGIC_VECTOR (13 down 0));
end cont_clk;

Attached files:

counterscheme.PNG (18 KB)

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Homework_Service @ Nightshift Guest 2020-12-27 21:21 #6527046

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity cont_clk is Port(
  enable: in std_logic;
  reset: in std_logic;
  clk: in std_logic;
  rco: out std_logic;
  q: out std_logic_vector(13 downto 0));
end cont_clk;
architecture Behavioral of cont_clk is
constant M: integer:=999999;
signal Data: std_logic_vector(13 downto 0):=(others => '0');
signal rco_buffer: std_logic:='0';
q <= Data;
rco_buffer <= '1' when to_integer(unsigned(Data)) = M else '0';
rco <= rco_buffer;
process begin
  wait until rising_edge(clk);
  if reset = '1' then
    Data <= (others => '0');
    if enable = '1' then
      if rco_buffer = '0' then
        Data <= std_logic_vector(unsigned(Data) +1);
      else
        Data <= (others => '0');
      end if;
    end if;
  end if;
end process;
end Behavioral;


Juan wrote:
> The counter should generate an end of count (rco) output signal that
> turns high every 1 millisecond

Depends on:
Clock frequency.

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Homework_Service @ Nightshift Guest 2020-12-27 21:38 #6527065

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Homework_Service @ Nightshift wrote:
> constant M: integer:=999999;

Too high. Choose Clock frequency <= 1/(1 ms/2**14) <= 16.38 MHz. And M 
<= 2**14-1.

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