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Forum: FPGA, VHDL & Verilog counter with signal enable (active high) and synchronous reset signal (active high)


von Juan (Guest)


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I'm trying to do the following task, but I need your help or some 
pointers:

Write a counter with signal enable (active high) and synchronous reset 
signal (active high) to a VHDL file (cont_clk.vhd).
The counter should generate an end of count (rco) output signal that 
turns high every 1 millisecond and which is active for one clock cycle 
(clk). It should also generate a count signal (q) of 14 bits.

Use the counter scheme (sequential circuit) described below.

The module should have the following entity declaration:

entity cont_clk is
 Port (enable: in STD_LOGIC;
 reset: in STD_LOGIC;
 clk: in STD_LOGIC;
 rco: out STD_LOGIC;
 q: out STD_LOGIC_VECTOR (13 down 0));
end cont_clk;

von Homework_Service @ Nightshift (Guest)


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1
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity cont_clk is Port(
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  enable: in std_logic;
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  reset: in std_logic;
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  clk: in std_logic;
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  rco: out std_logic;
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  q: out std_logic_vector(13 downto 0));
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end cont_clk;
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architecture Behavioral of cont_clk is
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constant M: integer:=999999;
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signal Data: std_logic_vector(13 downto 0):=(others => '0');
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signal rco_buffer: std_logic:='0';
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begin
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q <= Data;
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rco_buffer <= '1' when to_integer(unsigned(Data)) = M else '0';
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rco <= rco_buffer;
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process begin
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  wait until rising_edge(clk);
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  if reset = '1' then
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    Data <= (others => '0');
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  else
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    if enable = '1' then
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      if rco_buffer = '0' then
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        Data <= std_logic_vector(unsigned(Data) +1);
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      else
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        Data <= (others => '0');
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      end if;
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    end if;
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  end if;
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end process;
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end Behavioral;

Juan wrote:
> The counter should generate an end of count (rco) output signal that
> turns high every 1 millisecond

Depends on:
Clock frequency.

von Homework_Service @ Nightshift (Guest)


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Homework_Service @ Nightshift wrote:
> constant M: integer:=999999;

Too high. Choose Clock frequency <= 1/(1 ms/2**14) <= 16.38 MHz. And M 
<= 2**14-1.

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