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Forum: FPGA, VHDL & Verilog adc with fpga interface


von niclas (Guest)


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dear members, im new to fpga develpment what are things one should 
consider when interfacing adc chip to an fpga. Im interested to know 
thecircuit level stuffs like  how to choose fpga banks and so on? please 
share your experience. thanks

von -gb- (Guest)


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very unspecific ... there are huge differences between ADCs. Some have 
SPI Interface, others parallel SDR, some parallel DDR LVDS, some serial 
LVDS, ...

von niclas (Guest)


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sorry, lets take ad7626- serial as example
in the data sheet its specified


Differential Output Voltage, VOD 290 mV
Common-Mode Output Voltage, VOCM 1130  mV
Differential Input Voltage, VID 100 to 650 mV
Common-Mode Input Voltage, VICM 800 to 1575 mV

von Andreas (Guest)


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niclas wrote:
> dear members, im new to fpga develpment what are things one should
> consider when interfacing adc chip to an fpga. Im interested to know
> thecircuit level stuffs like  how to choose fpga banks and so on? please
> share your experience. thanks

Hey Niclas, it sounds a little like 'Do my homework ...'

What about some more details, what do you have in mind to do in your 
FPGA?

Best Regards,
Andreas

von -gb- (Guest)


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niclas wrote:
> sorry, lets take ad7626- serial as example
> in the data sheet its specified

This is a ADC with SPIish LVDS Interface and and CNV which can be driven 
as LVDS or CMOS.

To get the best performance:

Gnerate CLK and an CNV_enable with the FPGA, but retime CNV_enable with 
a low jitter Clock which does not come from the FPGA. This can be done 
with an external FF. Use DCO to capture the data D in the FPGA.

So ...
1
+---------+
2
| LOW     |                   +----------+
3
| JITTER  |                   |          |
4
| CLOCK   o---+-------------->i          |
5
+---------+   |               |          |
6
              |               |          |         
7
              |               |          |
8
              |               |   FPGA   |
9
+---------+   |               |          |
10
|  FLIP   i<--+               |          |
11
|  FLOP   i<--- CNV_enable ---o          |
12
|         o---+               |          |
13
+---------+   |               |          |
14
              |               |          |
15
              |               |          |
16
              |               |          |
17
+---------+   |               |          |
18
|         i<--+               |          |
19
|  ADC    i<------ CLK -------o          |
20
|  AD7626 o------- DCO -------i          |
21
|         o------- D ---------i          |
22
+---------+                   |          |
23
                              +----------+

CLK and CNC_enable have to be derived from the low jitter clock.
You could also gerenate CNV directly inside the FPGA without external 
FF, this is done on the evaluation board, but ... you may get a little 
bit poorer performance.

von niclas (Guest)


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Dear gb, thanks for the reply i can do the vhdl part. i can do the adc 
controlling and reading. thats not a problem. my question is how to 
choose FPGA bank to connect this ADC to FPGA

von -gb- (Guest)


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OK. Choose any bank. For the LVDS:

[quote]The 7 Series has different capabilities in the HR (High Range) 
and HP (High Performance) banks.

The HR banks use the LVDS_25 IOSTANDARD and if it as an output the VCCO 
must be 2.5V.

HR - LVDS_25 Output - VCCO must be 2.5V
HR - LVDS_25 Input and DIFF_TERM=TRUE  - VCCO must be 2.5V
HR - LVDS_25 Input and DIFF_TERM=FALSE - VCCO can be 1.8-3.3V

HP - LVDS Output - VCCO must be 1.8V
HP - LVDS Input and DIFF_TERM=TRUE - VCCO must be 1.8V
HP - LVDS Input and DIFF_TERM=FALSE - VCCO must be 1.8V[/quote]

Source: 
https://forums.xilinx.com/t5/Other-FPGA-Architecture/LVDS-in-HR-banks/td-p/206709

So CLK and CNV if it is generated in the FPGA have to connect to a HR 
Bank with VCCO=2.5 V. LVDS from a HP Bank may not be compatible with 
your ADC, check the Datasheets.
DCO and D can connect to a HR Bank with any allowed VCCO.

I use a similar ADC, the AD7960 and use as follows:
Low_jitter_clock CMOS -> Bank with VCCO=3.3 V
CNV_enable CMOS <- Bank with VCCO=3.3 V
CLK LVDS_25 <- Bank with VCCO=2.5V
DCO LVDS_25 -> Bank with VCCO=2.5V
D LVDS_25 -> Bank with VCCO=2.5V

But this is Xilinx/AMD. You did not name the FPGA you intend to use.

von niclas (Guest)


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i checked the ad7960 data sheet and below are the voltage levels i found

Differential Output Voltage, VOD RL = 290  mV
Common-Mode Output Voltage, VOCM RL = 1130 mV
Differential Input Voltage, VID 650 mV
Common-Mode Input Voltage, VICM 1575 mV

it may be stupid question..pardon me...My confusion is for  DCO and D 
which are inputs to fpga has VID 650mV as per ad7960 datsheet.. will the 
fpga able to capture this signal?
similarly for CLK output?

von -gb- (Guest)


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These

niclas wrote:
> Differential Input Voltage, VID 650 mV
> Common-Mode Input Voltage, VICM 1575 mV

are the maximum Values which are allowed for the ADC LVDS Inputs.

These

Differential Output Voltage, 290  mV
Common-Mode Output Voltage, 1130 mV

are the Values for the ADC LVDS Outputs -> FPGA Inputs.

LVDS_25 is defined here, Page 11:
https://www.xilinx.com/support/documentation/data_sheets/ds189-spartan-7-data-sheet.pdf

So yes, you can connect DCO and D directly from the ADC to the FPGA. 
But:
The FPGA Bank has to be an HR Bank and it has to be supplied with 
VCCO=2.5 V. You may also use the internal termination (set DIFF_TERM = 
TRUE) but you can also use an external 100 Ohm Resistor.

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