Forum: FPGA, VHDL & Verilog Abel to VHDL


von Jose (Guest)


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I'm trying to transfer some Abel code into VDHL. From the code it looks 
like an 8 bit parallel in parallel out shift register, I'm trying to 
draw a logic diagram first so that I can then transfer it to VHDL. Any 
reference or tips will be appreciated it.

//inputs
SPI0_CS3                    Pin 92        istype 'input';

// outputs
SPI0_MISO                Pin 66        istype 'com';

//Nodes
D0,D1,D2,D3,D4,D5,D6,D7        Node istype 'reg_d';

XEN = [Data0,Data1,Data2,Data3,Data4,Data5,Data6,Data7];

OUT = [D7..D0];

equations


D0.D = (!SPI0_CS3 & SPI0_MOSI) # (SPI0_CS3 & D0.Q);
D1.D = (!SPI0_CS3 & D0.Q) # (SPI0_CS3 & D1.Q);
D2.D = (!SPI0_CS3 & D1.Q) # (SPI0_CS3 & D2.Q);
D3.D = (!SPI0_CS3 & D2.Q) # (SPI0_CS3 & D3.Q);
D4.D = (!SPI0_CS3 & D3.Q) # (SPI0_CS3 & D4.Q);
D5.D = (!SPI0_CS3 & D4.Q) # (SPI0_CS3 & D5.Q);
D6.D = (!SPI0_CS3 & D5.Q) # (SPI0_CS3 & D6.Q);
D7.D = (!SPI0_CS3 & D6.Q) # (SPI0_CS3 & D7.Q);
OUT.CLK = SPI0_SCLK;

XEN.D = OUT.Q;
XEN.CLK = SPI0_CS3;

von Lothar M. (lkmiller) (Moderator)


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Jose wrote:
> it looks like an 8 bit parallel in parallel out shift register
It is all in one: a PiSo (parallel in serial out) and also a SiPo 
(serial in parallel out). As that it can be connected as a SPI slave 
device.

This SPI uses 3 signal wires:
1. the SPI0_SCLK is the SPI shift clock
2. the SPI0_CS3 is the low active Slave Select aka SS#
3. the SPI0_MISO is the "Master In Slave Out" seriel output data line
4. the SPI0_MOSI is the "Master Out Slave In" serial input data line

Knowing that you will find some similarities with that code:
http://www.lothar-miller.de/s9y/archives/31-SPI-Slave-im-CPLD.html
Try Google translate, but you will get the just by reading those few 
liens of code.


Jose wrote:
> I'm trying to draw a logic diagram first so that I can then transfer it
> to VHDL.
Do that.

: Edited by Moderator

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