EmbDev.net

Forum: FPGA, VHDL & Verilog Verilog: # Error loading design


von Vasily D. (zaebatsy)


Rate this post
0 useful
not useful
My code:

`timescale 10ns/100ps
module Verilog1;
wire [7:0]out;
reg [2:0]pin;
lab_1 g1(pin,out);
initial
begin
pin[1]=1'b0; pin[2]=1'b0; pin[3]=1'b0;
#3 pin[1]=1'b0; pin[2]=1'b0; pin[3]=1'b1;
#3 pin[1]=1'b0; pin[2]=1'b1; pin[3]=1'b0;
#3 pin[1]=1'b1; pin[2]=1'b0; pin[3]=1'b0;
#3 pin[1]=1'b0; pin[2]=1'b1; pin[3]=1'b1;
#3 pin[1]=1'b1; pin[2]=1'b1; pin[3]=1'b0;
#3 pin[1]=1'b1; pin[2]=1'b0; pin[3]=1'b1;
#3 pin[1]=1'b1; pin[2]=1'b1; pin[3]=1'b1;
end
initial
#50 $stop;
endmodule


My mistake:

# Reading C:/altera/10.0/modelsim_ase/tcl/vsim/pref.tcl
# do lab_1_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
#   vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying C:\altera\10.0\modelsim_ase\win32aloem/../modelsim.ini to 
modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied 
C:\altera\10.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
#
# vlog -vlog01compat -work work +incdir+C:/altera/labs 
{C:/altera/labs/lab_1.v}
# Model Technology ModelSim ALTERA vlog 6.5e Compiler 2010.02 Feb 27 
2010
# -- Compiling module lab_1
#
# Top level modules:
#   lab_1
#
# vlog -vlog01compat -work work +incdir+C:/altera/labs 
{C:/altera/labs/Verilog1.v}
# Model Technology ModelSim ALTERA vlog 6.5e Compiler 2010.02 Feb 27 
2010
# -- Compiling module Verilog1
# ** Warning: C:/altera/labs/Verilog1.v(8): [BSOB] - Bit-select into 
'pin' is out of bounds.
# ** Warning: C:/altera/labs/Verilog1.v(9): [BSOB] - Bit-select into 
'pin' is out of bounds.
# ** Warning: C:/altera/labs/Verilog1.v(10): [BSOB] - Bit-select into 
'pin' is out of bounds.
# ** Warning: C:/altera/labs/Verilog1.v(11): [BSOB] - Bit-select into 
'pin' is out of bounds.
# ** Warning: C:/altera/labs/Verilog1.v(12): [BSOB] - Bit-select into 
'pin' is out of bounds.
# ** Warning: C:/altera/labs/Verilog1.v(13): [BSOB] - Bit-select into 
'pin' is out of bounds.
# ** Warning: C:/altera/labs/Verilog1.v(14): [BSOB] - Bit-select into 
'pin' is out of bounds.
# ** Warning: C:/altera/labs/Verilog1.v(15): [BSOB] - Bit-select into 
'pin' is out of bounds.
#
# Top level modules:
#   Verilog1
#
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L 
cycloneive_ver -L rtl_work -L work -voptargs="+acc" 50
# vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L 
cycloneive_ver -L rtl_work -L work -voptargs=\"+acc\" -t 1ps 50
# ** Error: (vsim-3170) Could not find 
'C:\altera\labs\simulation\modelsim\rtl_work.50'.
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./lab_1_run_msim_rtl_verilog.do PAUSED at line 12

von Duke Scarring (Guest)


Rate this post
0 useful
not useful
Vasily D. wrote:
> # vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L
> cycloneive_ver -L rtl_work -L work -voptargs="+acc" 50
                                                      ^^
 
> # vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L
> cycloneive_ver -L rtl_work -L work -voptargs=\"+acc\" -t 1ps 50
                                                               ^^
 
> # ** Error: (vsim-3170) Could not find
> 'C:\altera\labs\simulation\modelsim\rtl_work.50'.
                                               ^^

Where did the '50' come from?
Why don't you use your testbench for simulation?
Why can't you ask a reasonable question?

Duke

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig