Forum: FPGA, VHDL & Verilog beginner question on gate level d flip flop simulation

I am trying to simulate the gate level classic d flip flop using 
verilog...
I know I could stick to its behavior level ... but that is not what I 
wanted to do ...

so far I have problem with the connections that wires output back into 
input ports... the error message generally reads like " invalid l-value 
"

I am aware that Icarus verilog simulator do not like output feedback, so
I am wondering if gate level simulation of classic d flip flop is even 
possible?

Jimmy Z. wrote:
> the error message generally reads like " invalid l-value "
Who generates that message with which code at what stage of processing?

> that Icarus verilog simulator do not like output feedback
I'm wondering why this should have something to do with "like" or 
"dislike"...