I am trying to simulate the gate level classic d flip flop using verilog... I know I could stick to its behavior level ... but that is not what I wanted to do ... so far I have problem with the connections that wires output back into input ports... the error message generally reads like " invalid l-value " I am aware that Icarus verilog simulator do not like output feedback, so I am wondering if gate level simulation of classic d flip flop is even possible?
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