Forum: FPGA, VHDL & Verilog How to properly multiply signed and unsigned

von signed unsigned (Guest)

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I stumbled over this several times now and would like to know how to 
properly do this in VHDL: I have a signed number and would like to 
multiply this with a positive factor (which is given by an unsigned). 
VHDL does not allow me to multiply signed with unsigned. What I did so 
- Convert unsigned into std_logic_vector
- Append leading zero bit
- Convert into signed. Since the first bit is always zero, I know no 
that the number is always positive, although represented with a signed 

This process works but seems retarded to me. I googled how to do this 
properly but surprisingly didn't find a lot, although I can't believe 
I'm the only one having to do this.

Any hint on how to write this in a clean proper way?

: Moved by Moderator
von Duke Scarring (Guest)

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signed unsigned schrieb:
> - Convert unsigned into std_logic_vector
Very bad idea, IMO.

I would convert the unsigned number also to signed and do than the 
If it's necessary to expand the vector size the function 'resize' will 

And I strongly suggest only use the signed/unsigned types from 
ieee.numeric_std.all library.



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