EmbDev.net

Forum: FPGA, VHDL & Verilog Synthesis: Mix of sync and async assignments to register


Synthesis: Mix of sync and async assignments to register
von if else what when (Guest)

Rate this post
• ▲ useful
▼ not useful 
During synthesis I get the following warning message stated:
"Mix of sync and async assignments to register 'Sig_Z' in module XXX in 
the same process may cause logic issues. Please split the sync and async 
parts into different processes."

The respective process is the following:
1
process(Sig_A, Sig_B)

2
begin

3
     for I in 0 to 3 loop

4
          Sig_Z(I) <= '0'

5
          if(Sig_A(I) > Sig_B(I) then

6
                    Sig_Z <= '1';

7
          end if;

8
     end loop;

9
end process;


I don't really get what the tool (Vivado) tries to tell me here. All the 
input signals (Sig_A, Sig_B) are coming from other flipflops, there is 
only one clock in the entire design. Synthesis completes fine and the 
result is working on my FPGA. However, I don't really trust this and 
asynchronous logic is not something I want to have in my design.
Does anybody recognize what I did wrong? Can I ignore this warning?

: Moved by Moderator
Report post Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Re: Synthesis: Mix of sync and async assignments to register
von Samuel C. (neoexacun)

Rate this post
• ▲ useful
▼ not useful 
You mix Sig_Z and Sig_Z(I).

Report post Edit Delete Quote selected text Reply Reply with quote
Re: Synthesis: Mix of sync and async assignments to register
von if else what when (Guest)

Rate this post
• ▲ useful
▼ not useful 
Ah shit, that was a mistake while copying it here, the code I used 
contains only Sig_Z(I)

1
process(Sig_A, Sig_B)

2
begin

3
     for I in 0 to 3 loop

4
          Sig_Z(I) <= '0'

5
          if(Sig_A(I) > Sig_B(I) then

6
                    Sig_Z(I) <= '1';

7
          end if;

8
     end loop;

9
end process;

Report post Edit Delete Quote selected text Reply Reply with quote
Re: Synthesis: Mix of sync and async assignments to register
von daniel__m (Guest)

Rate this post
• ▲ useful
▼ not useful 
hi,

the issue is not in the provided code.

Report post Edit Delete Quote selected text Reply Reply with quote
Re: Synthesis: Mix of sync and async assignments to register
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

Rate this post
• ▲ useful
▼ not useful 
if else what when schrieb:
> Can I ignore this warning?
Only when you know why you get the message and only if you want that 
what the message tells.

daniel__m schrieb:
> the issue is not in the provided code.
So it is.

Report post Edit Delete Quote selected text Reply Reply with quote
Re: Synthesis: Mix of sync and async assignments to register
von if else what when (Guest)

Rate this post
• ▲ useful
▼ not useful 
Lothar M. wrote:
> Only when you know why you get the message and only if you want that
> what the message tells.

Well that's why I was asking ;)

daniel__m wrote:
> the issue is not in the provided code.

Since tonight I doubt this because I was able to solve it with trial and 
error. The new code is this:
1
process(Sig_A, Sig_B)

2
begin

3
     for I in 0 to 3 loop

4
          -- Sig_Z(I) <= '0'  -- remove this line

5
          if(Sig_A(I) > Sig_B(I) then

6
                    Sig_Z(I) <= '1';

7
          else

8
                    Sig_Z(I) <= '0'      -- Put this in an else section instead of having it in front of the if statement

9
          end if;

10
     end loop;

11
end process;



In my opinion both pieces of code should do the same, simulation results 
are the same, testing on the FPGA results in the same. I didn't have 
time to check the synthesized logic so far.

Report post Edit Delete Quote selected text Reply Reply with quote
Watch this topic | Disable multi-page view
Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
No account? Register here.