During synthesis I get the following warning message stated:
"Mix of sync and async assignments to register 'Sig_Z' in module XXX in
the same process may cause logic issues. Please split the sync and async
parts into different processes."
The respective process is the following:
for I in 0 to 3 loop
Sig_Z(I) <= '0'
if(Sig_A(I) > Sig_B(I) then
Sig_Z <= '1';
I don't really get what the tool (Vivado) tries to tell me here. All the
input signals (Sig_A, Sig_B) are coming from other flipflops, there is
only one clock in the entire design. Synthesis completes fine and the
result is working on my FPGA. However, I don't really trust this and
asynchronous logic is not something I want to have in my design.
Does anybody recognize what I did wrong? Can I ignore this warning?