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Forum: FPGA, VHDL & Verilog Serializer verilog


von Atalin (Guest)


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Hi! I am writing a code for a serializer. The problem is that I have 
only 1s as output but I want to see the input bitstream, obviously. Do 
you have any suggestion? Thanks.

The code is the following:
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// Serializer
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`timescale 1ns / 1ps
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module serializer (data_in, send, clk, load, rst, data_out);
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input wire [11:0] data_in;
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input wire send, clk, load, rst;
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output reg data_out;
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reg [11:0] temp_data_out;
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integer i;
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integer j;
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always @ (posedge clk) 
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begin
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  if (rst) begin
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    data_out <= 1'b0;
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    temp_data_out <= 12'b0;
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  end
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  else if (load)
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    for(i=0; i<12; i=i+1)
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      temp_data_out[i] <= data_in[i];
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  else if (send)
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    for(j=0; j<12; j=j+1)
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      data_out <= temp_data_out[j];
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    //data_out <= temp_data_out[0];
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    //temp_data_out <= {temp_data_out[10:0], 1'b0};
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end
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endmodule //end module serializer

The testbench is
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`include "serializer.v"
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`timescale 1ns / 1ps
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module serializer_tb();
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// Declare inputs as regs and outputs as wires
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reg [11:0] data_in;
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reg send, clk, load, rst;
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wire data_out;
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// Initialize all variables
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initial begin          
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  clk = 1;       // initial value of clock
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  rst = 1;       // initial value of reset
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  load = 0;
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  send = 0;
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  data_in = 12'b110110110110;
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  #15 rst = 0;   // De-assert the reset
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  #13 load = 1;
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  #15 load = 0;
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  #5 send = 1;
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  #125 send = 0;
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  #10 data_in = 12'b100100010001;
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  #10 load = 1;
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  #15 load = 0;
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  #5 send = 1;
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  #125 send = 0;
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end
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// Clock generator
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always begin
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  #5 clk = ~clk; // Toggle clock every 5 ns - 100 MHz
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end
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// Connect DUT to test bench
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serializer U_serializer (data_in, send, clk, load, rst, data_out);
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endmodule

von Lothar M. (lkmiller) (Moderator)


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Have a look what a for loop does in Verilog: it produces parallel 
hardware. It looks like you expect something entirely different.

BTW:
I assume this here:
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    for(i=0; i<12; i=i+1)
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      temp_data_out[i] <= data_in[i];
Could be cut down to one line:
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      temp_data_out <= data_in;
But I may be completely wrong because I'm doing VHDL usually... ;-)

: Edited by Moderator
von Klakx (Guest)


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you toggle "load" at #13 and #15, but your clock toggles with #5 (and 
rising edges with 10). I think you will miss easily signals in that 
style

improve your testbench with:
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@(posedge clk) 
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load = 1;
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@(posedge clk)
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load = 0;

furthermore:
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for(j=0; j<12; j=j+1)
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      data_out <= temp_data_out[j];
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// is the same like
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      data_out <= temp_data_out[11];
In a N-serializer you have to use a 1-bit clock and your inputs stays at 
the correct time every N cycles or for N cycles.

von Atalin (Guest)


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Thank you! I tried to modify that line but nothig has changed...

von Atalin (Guest)


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Hi! For what concern the tesbench, in the simulation result I can see 
that when load is high, it returns to 0 after 15 ns. So, it is high for 
at least 1 clock cycle.

If I write
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      data_out <= temp_data_out[11];

how I can see as output the whole bit stream? In this way I can see only 
temp_data_out[11] and not all the bits in that array

von VHDL hotline (Guest)


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Why you commented this line?
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    //temp_data_out <= {temp_data_out[10:0], 1'b0};

This is basically what the serializer should do, shifting out the bits. 
Also, in hardware the for loops are unrolled and so all happens in one 
clock cycle and the last assignment wins. In your case, the second for 
loop always results to 'data_out <= temp_data_out[11]'. Discard the for 
loops and try like this:
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always @ (posedge clk) 
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begin
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  if (rst) begin
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    data_out <= 1'b0;
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    temp_data_out <= 12'b0;
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  end
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  else if (load)
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      temp_data_out <= data_in;  //take over the vector
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  else if (send)
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      data_out <= temp_data_out[11];  //assert the MSBit of the vector at output
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      temp_data_out <= {temp_data_out[10:0], 1'b0}; //shift the vector by one bit per cycle
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end

von Atalin (Guest)


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Yes you are absolutely righ, I commented that line because I was not 
sure (I am new in programming so maybe it is easier for me think with 
for loop..!) but I was thinking again about it and you confirmed my 
thought. Thank you very much!

von Lothar M. (lkmiller) (Moderator)


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Atalin wrote:
> I am new in programming
Don't think you are "programming" like a software programmer writes a 
program for a computing device. What you are doing is "describing" 
hardware using a HDL (Hardware Description Language). So at first you 
must have a "picture" of that hardware on a sheet of paper or at least 
in your brain. Then you can describe it with Verilog (or VHDL or 
whatsoever).

By doing this don't let you betray by "false friends" like that 
"for-loop" in the posts above.

VHDL hotline wrote:
> This is basically what the serializer should do, shifting out the bits
But of course this serializer also could be done with a 12:1 
multiplexer. So with each clock a counter must count up and then this 
counter can be used for indexing the desired bit.

von Atalin (Guest)


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Hi guys! I am here again for asking some help. Here I have the testbench 
of the serializer (I slightly modify it in order to have random bits as 
input). I would like to add a kind of receiver (like a serial-in 
parallel-out register) in order to check automatically if the input 
parallel data are equal to the output. How can I do this? Thanks
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`include "serializer.v"
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`timescale 1ns / 1ps
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module serializer_tb();
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// Declare inputs as regs and outputs as wires
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reg [11:0] data_in;
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reg send, clk, load, rst;
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wire data_out;
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// Initialize all variables
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initial begin          
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  clk = 1;       // initial value of clock
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  rst = 1;       // initial value of reset
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  load = 0;
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  send = 0;
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  #15 rst = 0;   // De-assert the reset
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  forever begin
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    foreach(data_in[ii]) data_in[ii] = $urandom;
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    #13 load = 1;
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    #15 load = 0;
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    #5 send = 1;
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    #85 send = 0;
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  end
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end
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// Clock generator
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always begin
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  #5 clk = ~clk; // Toggle clock every 5 ns - 100 MHz
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end
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// Connect DUT to test bench
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serializer U_serializer (data_in, send, clk, load, rst, data_out);
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endmodule

von Atalin (Guest)


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I find out this solution, maybe someone needs it too :)
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 initial begin          
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  clk = 1;       // initial value of clock
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  rst = 1;       // initial value of reset
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  load = 0;
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  send = 0;
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  #15 rst = 0;   // De-assert the reset
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  forever begin
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    foreach(data_in[j]) data_in[j] = $urandom;
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    #13 load = 1;
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    #15 load = 0;
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    #5 send = 1;
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    #20          //header
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    for(i=0; i<12; i=i+1) begin
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      #5 reg_sipo[11-i] <= data_out;
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      end
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    #5 send = 0;
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    if(reg_sipo == data_in) check = 0;
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    else check = 1;
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  end
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end

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