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Forum: FPGA, VHDL & Verilog Gray counter verilog


von Gio97 (Guest)


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Hi guys!
I want to write the verilog code for a 8-bit gray counter. I added in 
attach the code and the testbech. For some reason I cannot understand, I 
cannot see as outputs the counting, I have only "z" value as output. 
Please could you help me? Thank you very much!

von W. M. (thematsche)


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Try this out with

   iverilog gray_counter_tb.v -o gray_counter

regards

von Gio97 (Guest)


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This is not very clear. Where is the error? Thanks

von VHDL hotline (Guest)


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The order of ports in your DUT does not match the order in the 
instantiation. To avoid such issues, you should connect the ports by 
name, i.e. .clk(clk).

von Gio97 (Guest)


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Thank you! I solved the problem. I want that the counter stops when it 
reaches the maximum value until I give a new clear signal. Hence, I 
added an "if" but it doesn't work because the counter keeps counting and 
then stops when it reaches "10000000". Could you help me?
The code is presented here

 module gray_counter (clk, clear, count, out);

input clk, clear, count; 
output wire [7:0] out;

wire clk;
wire clear;
wire count;
reg [7:0] temp_out;

always @ (posedge clk)
begin
  if(clear) 
    temp_out <= 8'b00000000;  
  else if(count && temp_out != 8'b11111111) 
    temp_out <= temp_out + 1'b1;
end

assign out = {temp_out[7], (temp_out[7]^temp_out[6]), (temp_out[6]^temp_out[5]), (temp_out[5]^temp_out[4]), (temp_out[4]^temp_out[3]), (temp_out[3]^temp_out[2]), (temp_out[2]^temp_out[1]), (temp_out[1]^temp_out[0])};

endmodule //end module gray_counter

: Edited by Moderator
von Gio97 (Guest)


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I tried to write
  else if(count && out != 8'b11111111)
    temp_out <= temp_out + 1'b1;
instead of
  else if(count && temp_out != 8'b11111111)
    temp_out <= temp_out + 1'b1;
and now it seems working but I cannot understand why.

: Edited by Moderator
von Klakx (Guest)


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I think it only valid to read on an output signal if you declare it 
"output reg.."
//output wire [7:0] out;
output reg [7:0] out;

however, out and temp_out are also different by logic.

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