// 8-bit gray counter with enable and active-high reset `timescale 1ns / 1ps module gray_counter (out, enable, clk, rst); input clk, rst, enable; output wire [7:0] out; wire enable; wire clk; wire rst; reg [7:0] count; always @ (posedge clk) begin if(rst == 1'b1) begin count <= #1 1'b0; end else if(enable == 1'b1) begin count <= #1 count + 1'b1; end assign out = {count[7], (count[7]^count[6]), (count[6]^count[5]), (count[5]^count[4]), (count[4]^count[3]), (count[3]^count[2]), (count[2]^count[1]), (count[1]^count[0])}; end endmodule //end module gray_counter