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Forum: FPGA, VHDL & Verilog Why can't I set a (genvar) outside the control section of a loop?


von Kevin S. (kvnsmnsn)


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I just wrote a design in Verilog that takes two operands as input, 
(leftOp) and (rightOp),  and outputs one operand, (result), where the 
common length of all operands is defined by parameter (nmBits), that 
defaults to 1. I want to loop through the bits in (result), and make 
each the exclusive or of the bit on the opposite side on (leftOp) and 
(rightOp). My code is:
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module rbwx ( result, leftOp, rightOp);
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parameter nmBits = 1;
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integer highBit  = nmBits - 1;
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output [ highBit:0] result;
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input  [ highBit:0] leftOp;
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input  [ highBit:0] rightOp;
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genvar ix, opp;
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for (ix = 0; ix < nmBits; ix = ix + 1)
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begin
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  opp = highBit - ix;
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  xor2 x2( result[ ix], leftOp[ opp], rightOp[ opp]);
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end
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endmodule
When I run Icarus on this I get:
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D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o rbwx.out rbwx.sv
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rbwx.sv:12: syntax error
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rbwx.sv:12: error: Invalid module instantiation
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D:\Hf\Verilog\Unpacked\Common>
So my design is generating a syntax error right where I assign (opp) to 
the difference between (highBit) and (ix). Why can't I do this, since 
(opp) is defined as a (genvar)? Can I only use (genvar)s in the control 
section of a loop?

von Klakx (Guest)


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I think there should also be a generate / endgenerate statement placed 
around the for loop.

von Kevin S. (kvnsmnsn)


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Klakx wrote:
> I think there should also be a generate / endgenerate statement placed
> around the for loop.

Accordingly I copied "rbwx.sv" to "klakx.sv" to get:
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module klakx ( result, leftOp, rightOp);
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parameter nmBits = 1;
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integer highBit  = nmBits - 1;
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output [ highBit:0] result;
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input  [ highBit:0] leftOp;
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input  [ highBit:0] rightOp;
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genvar ix, opp;
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generate
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  for (ix = 0; ix < nmBits; ix = ix + 1)
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  begin
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    opp = highBit - ix;
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    xor2 x2( result[ ix], leftOp[ opp], rightOp[ opp]);
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  end
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endgenerate
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endmodule
and then I tried this with Icarus and got:
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D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o klakx.out klakx.sv
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klakx.sv:13: syntax error
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klakx.sv:13: error: Invalid module instantiation
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D:\Hf\Verilog\Unpacked\Common>
Looks like the enclosing the (for) loop with (generate) and 
(endgenerate) didn't fix the problem.

von Klakx (Guest)


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"syntax error" ... icarus is very shy compiler...

localparam is the solution:
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module klakx ( result, leftOp, rightOp);
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parameter nmBits = 1;
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localparam integer highBit  = nmBits - 1; // here
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output [ highBit:0] result;
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input  [ highBit:0] leftOp;
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input  [ highBit:0] rightOp;
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genvar ix; // remove opp here
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generate
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  for (ix = 0; ix < nmBits; ix = ix + 1)
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  begin
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    localparam opp = highBit - ix; // here
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    xor2 x2( result[ ix], leftOp[ opp], rightOp[ opp]);
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  end
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endgenerate
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endmodule

von Kevin S. (kvnsmnsn)


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Klakx, thanks for that last little bit! It's working just fine now.

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