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Forum: FPGA, VHDL & Verilog Why can't I set a (genvar) outside the control section of a loop?


von Kevin S. (kvnsmnsn)


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I just wrote a design in Verilog that takes two operands as input, 
(leftOp) and (rightOp),  and outputs one operand, (result), where the 
common length of all operands is defined by parameter (nmBits), that 
defaults to 1. I want to loop through the bits in (result), and make 
each the exclusive or of the bit on the opposite side on (leftOp) and 
(rightOp). My code is:
module rbwx ( result, leftOp, rightOp);
parameter nmBits = 1;
integer highBit  = nmBits - 1;
output [ highBit:0] result;
input  [ highBit:0] leftOp;
input  [ highBit:0] rightOp;

genvar ix, opp;

for (ix = 0; ix < nmBits; ix = ix + 1)
begin
  opp = highBit - ix;
  xor2 x2( result[ ix], leftOp[ opp], rightOp[ opp]);
end

endmodule
When I run Icarus on this I get:
D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o rbwx.out rbwx.sv
rbwx.sv:12: syntax error
rbwx.sv:12: error: Invalid module instantiation

D:\Hf\Verilog\Unpacked\Common>
So my design is generating a syntax error right where I assign (opp) to 
the difference between (highBit) and (ix). Why can't I do this, since 
(opp) is defined as a (genvar)? Can I only use (genvar)s in the control 
section of a loop?

von Klakx (Guest)


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I think there should also be a generate / endgenerate statement placed 
around the for loop.

von Kevin S. (kvnsmnsn)


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Klakx wrote:
> I think there should also be a generate / endgenerate statement placed
> around the for loop.

Accordingly I copied "rbwx.sv" to "klakx.sv" to get:
module klakx ( result, leftOp, rightOp);
parameter nmBits = 1;
integer highBit  = nmBits - 1;
output [ highBit:0] result;
input  [ highBit:0] leftOp;
input  [ highBit:0] rightOp;

genvar ix, opp;

generate
  for (ix = 0; ix < nmBits; ix = ix + 1)
  begin
    opp = highBit - ix;
    xor2 x2( result[ ix], leftOp[ opp], rightOp[ opp]);
  end
endgenerate

endmodule
and then I tried this with Icarus and got:
D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o klakx.out klakx.sv
klakx.sv:13: syntax error
klakx.sv:13: error: Invalid module instantiation

D:\Hf\Verilog\Unpacked\Common>
Looks like the enclosing the (for) loop with (generate) and 
(endgenerate) didn't fix the problem.

von Klakx (Guest)


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"syntax error" ... icarus is very shy compiler...

localparam is the solution:
module klakx ( result, leftOp, rightOp);
parameter nmBits = 1;
localparam integer highBit  = nmBits - 1; // here
output [ highBit:0] result;
input  [ highBit:0] leftOp;
input  [ highBit:0] rightOp;

genvar ix; // remove opp here

generate
  for (ix = 0; ix < nmBits; ix = ix + 1)
  begin
    localparam opp = highBit - ix; // here
    xor2 x2( result[ ix], leftOp[ opp], rightOp[ opp]);
  end
endgenerate

endmodule

von Kevin S. (kvnsmnsn)


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Klakx, thanks for that last little bit! It's working just fine now.

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