I just wrote a design in Verilog that takes two operands as input, 
(leftOp) and (rightOp),  and outputs one operand, (result), where the 
common length of all operands is defined by parameter (nmBits), that 
defaults to 1. I want to loop through the bits in (result), and make 
each the exclusive or of the bit on the opposite side on (leftOp) and 
(rightOp). My code is:

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module rbwx ( result, leftOp, rightOp);

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parameter nmBits = 1;

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integer highBit  = nmBits - 1;

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output [ highBit:0] result;

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input  [ highBit:0] leftOp;

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input  [ highBit:0] rightOp;

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genvar ix, opp;

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for (ix = 0; ix < nmBits; ix = ix + 1)

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begin

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  opp = highBit - ix;

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  xor2 x2( result[ ix], leftOp[ opp], rightOp[ opp]);

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end

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endmodule

When I run Icarus on this I get:

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D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o rbwx.out rbwx.sv

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rbwx.sv:12: syntax error

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rbwx.sv:12: error: Invalid module instantiation

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D:\Hf\Verilog\Unpacked\Common>

So my design is generating a syntax error right where I assign (opp) to 
the difference between (highBit) and (ix). Why can't I do this, since 
(opp) is defined as a (genvar)? Can I only use (genvar)s in the control 
section of a loop?