Can a function take a boolean argument?

Kevin S. OP #6379858
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I've got a function that I'd like to behave slightly differently 
depending on the value of a boolean argument, an argument whose value 
can be either (true) or (false). I tried:
1
function automatic integer fillSubtree;

2
    input integer vrtcl;

3
    input integer hrzntl;

4
    input boolean pstve;

5
...

6
endfunction

but then when I used Icarus to simulate it, I got the error message:
1
lessThan.sv:34: syntax error

Line 34 is the line where I declare variable (pstve). Is there a way to 
pass a boolean argument to a function, or am I going to have to declare 
an (enum) that has values (true) and (false)?
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Dussel Guest #6379871
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Which language? Verilog? I don't know Verilog very well, but you can 
change the order of the inputs.
1
function automatic integer fillSubtree;

2
    input integer vrtcl;

3
    input boolean pstve;

4
    input integer hrzntl;

5
...

6
endfunction

If the line of the error changes, the declaration is the problem, if the 
line stays the same, it is something else.

Is it boolean or bool?
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Kevin S. OP #6379935
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Dussel wrote:
> Which language? Verilog? I don't know Verilog very well, but you
> can
> change the order of the inputs.function automatic integer fillSubtree;
>     input integer vrtcl;
>     input boolean pstve;
>     input integer hrzntl;
> ...
> endfunction
> If the line of the error changes, the declaration is the problem, if the
> line stays the same, it is something else.
>
> Is it boolean or bool?

Everything I've done recently has been in Verilog. I tried (bool) 
instead of (boolean); I got the same error message. I tried putting the 
(pstve) declaration first; I got the same error message.
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sid Guest #6380538
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I think you should rather quote us the lines 30-40 of your code..

If as you said the error stays the same,
I'd assume line 34 or adjacent are indeed the culprit.
a simple unidentified typo may be all that needs to be fixed.

Sometimes a simple logical error
if you changed the function in whichever way,
make sure the calls to that functions are resolveable
(number, type and order of parameters for example)
I don't know verilog tbh.. but no matter what language,
function calls are usually strict about that,
so chances are that holds true for verilog as well, right ;)


'sid
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Kevin S Guest #6380837
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Okay, I isolated the problem in a little piece of code I wrote:
1
module sid ();

2


3
function integer execOp;

4
    input integer left;

5
    input integer right;

6
    input boolean add;

7
  begin

8
    execOp = op == add ? left + right : left * right;

9
  end

10
endfunction

11


12
endmodule

Then when I use Icarus to simulate it I get:
1
D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o sid.out sid.sv

2
sid.sv:6: syntax error

3
sid.sv:3: error: Syntax error defining function.

4


5
D:\Hf\Verilog\Unpacked\Common>

And switching the order of arguments gives:
1
module sid_sw ();

2


3
function integer execOp;

4
    input boolean add;

5
    input integer left;

6
    input integer right;

7
  begin

8
    execOp = op == add ? left + right : left * right;

9
  end

10
endfunction

11


12
endmodule

When I execute Icarus I get:
1
D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o sid_sw.out sid_sw.sv

2
sid_sw.sv:4: syntax error

3
sid_sw.sv:3: error: Syntax error defining function.

4


5
D:\Hf\Verilog\Unpacked\Common>

Note that the syntax error is now on line 4, so declaring a boolean 
input causes the syntax error both times. Any ideas why, anyone?
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Kevin S. OP #6380917
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Wow, that was incredibly sloppy! Not only did I forget to log in prior 
to posting (causing me to be identified as a guest), but I also
included a variable in both source codes that was never declared. So I'm 
repeating that post with all those problems fixed.

Okay, I isolated the problem in a little piece of code I wrote:
1
module sid ();

2


3
function integer execOp;

4
    input integer left;

5
    input integer right;

6
    input boolean add;

7
  begin

8
    execOp = add ? left + right : left * right;

9
  end

10
endfunction

11


12
endmodule

Then when I use Icarus to simulate it I get:
1
D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o sid.out sid.sv

2
sid.sv:6: syntax error

3
sid.sv:3: error: Syntax error defining function.

4


5
D:\Hf\Verilog\Unpacked\Common>

And switching the order of arguments gives:
1
module sid_sw ();

2


3
function integer execOp;

4
    input boolean add;

5
    input integer left;

6
    input integer right;

7
  begin

8
    execOp = add ? left + right : left * right;

9
  end

10
endfunction

11


12
endmodule

When I execute Icarus I get:
1
D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o sid_sw.out sid_sw.sv

2
D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o sid_sw.out sid_sw.sv

3
sid_sw.sv:4: syntax error

4
sid_sw.sv:3: error: Syntax error defining function.

5


6
D:\Hf\Verilog\Unpacked\Common>

Note that the syntax error is now on line 4, so declaring a boolean 
input causes the syntax error both times. Any ideas why, anyone?
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