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Forum: FPGA, VHDL & Verilog Can a function take a boolean argument?


von Kevin S. (kvnsmnsn)


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I've got a function that I'd like to behave slightly differently 
depending on the value of a boolean argument, an argument whose value 
can be either (true) or (false). I tried:
function automatic integer fillSubtree;
    input integer vrtcl;
    input integer hrzntl;
    input boolean pstve;
...
endfunction
but then when I used Icarus to simulate it, I got the error message:
lessThan.sv:34: syntax error
Line 34 is the line where I declare variable (pstve). Is there a way to 
pass a boolean argument to a function, or am I going to have to declare 
an (enum) that has values (true) and (false)?

von Dussel (Guest)


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Which language? Verilog? I don't know Verilog very well, but you can 
change the order of the inputs.
function automatic integer fillSubtree;
    input integer vrtcl;
    input boolean pstve;
    input integer hrzntl;
...
endfunction
If the line of the error changes, the declaration is the problem, if the 
line stays the same, it is something else.

Is it boolean or bool?

von Kevin S. (kvnsmnsn)


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Dussel wrote:
> Which language? Verilog? I don't know Verilog very well, but you
> can
> change the order of the inputs.function automatic integer fillSubtree;
>     input integer vrtcl;
>     input boolean pstve;
>     input integer hrzntl;
> ...
> endfunction
> If the line of the error changes, the declaration is the problem, if the
> line stays the same, it is something else.
>
> Is it boolean or bool?

Everything I've done recently has been in Verilog. I tried (bool) 
instead of (boolean); I got the same error message. I tried putting the 
(pstve) declaration first; I got the same error message.

von sid (Guest)


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I think you should rather quote us the lines 30-40 of your code..

If as you said the error stays the same,
I'd assume line 34 or adjacent are indeed the culprit.
a simple unidentified typo may be all that needs to be fixed.

Sometimes a simple logical error
if you changed the function in whichever way,
make sure the calls to that functions are resolveable
(number, type and order of parameters for example)
I don't know verilog tbh.. but no matter what language,
function calls are usually strict about that,
so chances are that holds true for verilog as well, right ;)


'sid

von Kevin S (Guest)


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Okay, I isolated the problem in a little piece of code I wrote:
module sid ();

function integer execOp;
    input integer left;
    input integer right;
    input boolean add;
  begin
    execOp = op == add ? left + right : left * right;
  end
endfunction

endmodule
Then when I use Icarus to simulate it I get:
D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o sid.out sid.sv
sid.sv:6: syntax error
sid.sv:3: error: Syntax error defining function.

D:\Hf\Verilog\Unpacked\Common>
And switching the order of arguments gives:
module sid_sw ();

function integer execOp;
    input boolean add;
    input integer left;
    input integer right;
  begin
    execOp = op == add ? left + right : left * right;
  end
endfunction

endmodule
When I execute Icarus I get:
D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o sid_sw.out sid_sw.sv
sid_sw.sv:4: syntax error
sid_sw.sv:3: error: Syntax error defining function.

D:\Hf\Verilog\Unpacked\Common>
Note that the syntax error is now on line 4, so declaring a boolean 
input causes the syntax error both times. Any ideas why, anyone?

von Kevin S. (kvnsmnsn)


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Wow, that was incredibly sloppy! Not only did I forget to log in prior 
to posting (causing me to be identified as a guest), but I also
included a variable in both source codes that was never declared. So I'm 
repeating that post with all those problems fixed.

Okay, I isolated the problem in a little piece of code I wrote:
module sid ();

function integer execOp;
    input integer left;
    input integer right;
    input boolean add;
  begin
    execOp = add ? left + right : left * right;
  end
endfunction

endmodule
Then when I use Icarus to simulate it I get:
D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o sid.out sid.sv
sid.sv:6: syntax error
sid.sv:3: error: Syntax error defining function.

D:\Hf\Verilog\Unpacked\Common>
And switching the order of arguments gives:
module sid_sw ();

function integer execOp;
    input boolean add;
    input integer left;
    input integer right;
  begin
    execOp = add ? left + right : left * right;
  end
endfunction

endmodule
When I execute Icarus I get:
D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o sid_sw.out sid_sw.sv
D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o sid_sw.out sid_sw.sv
sid_sw.sv:4: syntax error
sid_sw.sv:3: error: Syntax error defining function.

D:\Hf\Verilog\Unpacked\Common>
Note that the syntax error is now on line 4, so declaring a boolean 
input causes the syntax error both times. Any ideas why, anyone?

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