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Forum: FPGA, VHDL & Verilog Double registering


von SparkyT (Guest)


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Hi,
am using the bellow SPI master as an example.

http://www.lothar-miller.de/s9y/categories/45-SPI-Master

and it got me thinking. The FPGA is producing MOSI, CLK and CSn.
But it is reading in MISO.
Do I need to double register? Would that mess up shifting in of bits?

Thanks

von Lothar M. (lkmiller) (Moderator)


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SparkyT wrote:
> The FPGA is producing MOSI, CLK and CSn. But it is reading in MISO.
Yes, that is SPI: concatenated shift registers.

> Do I need to double register?
No, because MISO is for sure stable at the sampling points, because in 
the waveform there in 
http://www.lothar-miller.de/s9y/archives/50-Einfacher-SPI-Master-Mode-0.html 
you see: due to SPI mode 0 both MOSI and MISO change at the falling 
SCLK. Their values are stable at the the rising edge of SCLK at which 
they are sampled.

> The FPGA is producing MOSI, CLK and CSn.
It produces MOSI, SCLK and SSn.
Together with MISO are that the names of the signals used by a SPI 
interface. And to discuss clearly I urge to use that signal names. 
Otherwise somone may muddle up CLK (the one and only master clock in the 
FPGA design) with some signals named "clock" like SCLK (SPI) or SCL 
(I2C) or some SHCK (shift clock) or whatever else.

von SparkyT (Guest)


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Thanks for the reply, and sorry for confusing the names.
I think i understand now, the SPI master is using the one and only 
CLK(fast) of the system. When sampling MISO with the SCLK(slow), it 
implies many samples of the fast clock.

Am working on a configurable SPI master at runtime.

- SCLK speed
- SPI messaging legth
- CPOL and CPHA
- SSn hold times

Is there anything else to consider?

T

von Lothar M. (lkmiller) (Moderator)


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SparkyT wrote:
> I think i understand now
So it seems... ;-)

> Am working on a configurable SPI master at runtime.
Have a look at the improved implementation at 
https://www.emb4fun.de/fpga/components/index.html (bottom of page)

: Edited by Moderator
von SparkyT (Guest)


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Thanks for the tip

T

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