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Forum: FPGA, VHDL & Verilog ISE synthesis warning


von changseon (Guest)


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I did the synthesis with ISE, but I was warned that 'Underlying logic 
will be removed'.
WARNING:Xst:2972 All outputs of instance <M2> of block <multiply> are 
unconnected in block <encoder>. Underlying logic will be removed.

I didnt solve this problem please help me

thank you for reading

von Lothar M. (lkmiller) (Moderator)


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changseon wrote:
> All outputs of instance <M2> of block <multiply> are unconnected in
> block <encoder>. Underlying logic will be removed.
I find that message tells very clear whats going on.
Because the synthesizer ignores comments, it sees your designs IO ports 
like that:
module encoder(
    input start_input,
    input stop,
    input clk,
    output stop_reg,
    output reg start_reg
);
Thre inputs and two outputs. So it only has to implement hardware for 
the two outputs stop_reg and the start_reg. And getting rid of the 
unnecessary code, this is enough to handle those two outputs:
assign stop_reg=stop;

always@(posedge clk)begin
  if(stop)
    start_reg<=0;
  else
    start_reg<=start_input;
end
All the other code does not affect any of the outputs of the design, so 
all the other code can be ignored. and thats what the synthesizer 
does...

Conclusion:
Because your design does not have any ouptuts connected to any of the 
internal signals there is no need to implement any internal logic. If 
you want to get hardware, then you have to connect it to the outer world 
somehow.

: Edited by Moderator

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