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Forum: FPGA, VHDL & Verilog Booth Multiplier Verilog code not working


von Prabhanshu (Guest)


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In the verilog file attached, when I simulate it, for some reason the 
eqz port always remains at dont care. It is supposed to be HIGH when 
count becomes 0. But for some reason nothing seems to trigger it. I 
can't figure out what the problem is.
Can someone debug the code and tell me what could be the problem?
Thankyou.

von Lothar M. (lkmiller) (Moderator)


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Prabhanshu wrote:
> It is supposed to be HIGH when count becomes 0
And: did you see count becoming 0 at any time in your simulation?

von Prabhanshu (Guest)


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I found the problem with eqz, i had made that port as output instead of 
input in controller. However the output of the multiplier is still 
wrong. Any help would be appreciated.

von Prabhanshu (Guest)


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Thankyou for responding Lothar M. The problem has been solved. The only 
issue remaining is if we can show decimal equivalent of 2's complement 
number in $monitor command.

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