EmbDev.net

Forum: FPGA, VHDL & Verilog VHDL: Synchronizing an asynchronous interface without a clock


VHDL: Synchronizing an asynchronous interface without a clock
von Alex K. (ak55)

Attached files:
Rate this post
• ▲ useful
▼ not useful 
I am trying to implement a custom bridge between a clocked synchronous 
interface and an asynchronous interface which is not clocked. I am 
having difficuties in synchronizing the asnychronous interface. I want 
to synchronize it to avoid timing issues in Quartus.

The signals like ebi_cs_n, ebi_bs1_n are misinterpreted as clocks by the 
tool when left asynchronous. I want to avoid that.

Please find the code in attachments.

How can I get a synchronous behavior of the synchronous interface. Or is 
there a better way to kepe the asynchronous interface without running 
into metastability  issues.

P.S. Unfortunately the asynchrnonous interface comes without a clock. 
And that is why I want to turn into a clean code having a synchronous 
behavior

: Edited by User
Report post Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Re: VHDL: Synchronizing an asynchronous interface without a clock
von Klakx (Guest)

Rate this post
• ▲ useful
▼ not useful 
if your EBI runs at ..50 MHz or lower then a reliable approach can be 
achieved by using a high oversampling clock, like 200 MHz.

Report post Edit Delete Quote selected text Reply Reply with quote
Re: VHDL: Synchronizing an asynchronous interface without a clock
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

Rate this post
• ▲ useful
▼ not useful 
Alex K. wrote:
> The signals like ebi_cs_n, ebi_bs1_n are misinterpreted as clocks by the
> tool when left asynchronous.
You have written them in a way, they must be "clocks" to a latch.

> I want to avoid that.
Indeed you should avoid latches unless you want them. And if you want 
them e.g. for the storing signal s_TSREV then you must accept that the 
toolchain invokes some kind of clock for those signals.

The other way (as already said) is to oversample and synchronize the 
control signals cs, we, bs... and work with the synchronized signals 
further on (edge detection for storing/latching the bus value...).

BTW: where did you find this strange kind of code?
1
   process(avln_clk, avln_reset)

2
       variable sync_rst   : std_logic;

3
   begin

4
       if falling_edge(avln_clk) then 

5
           sync_rst    := not avln_reset; 

6
       end if;

7
       if rising_edge(avln_clk) then 

8
           nReset    <= sync_rst;

9
           

10
       end if;

11
   end process;

This is a very uncommon way to tighten up the timing requirements to the 
design. Or with other words: do not use both edges of a clock in 1 
design. Additionally the avln_reset ist not needed in the sensitivity 
list, because the result of the process only depends on the avln_clk.

Report post Edit Delete Quote selected text Reply Reply with quote
Watch this topic | Disable multi-page view
Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
No account? Register here.