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Forum: FPGA, VHDL & Verilog 4Byte sequence to int


von Marthy .D (Guest)


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Hello guys!
How can we convert a 4 byte to int in VHDL ?
I have for example these 4 bytes that I want to convert to int .

hex:
[3E 29 C3 39]

Otherwise how do we convert it manually ?

von Jörg W. (dl8dtl) (Moderator)


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Combine them into a 32-bit std_logic_vector, from there, convert it to 
signed or unsigned integer.

http://www.lothar-miller.de/s9y/categories/16-Numeric_Std

von Lothar M. (lkmiller) (Moderator)


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Marthy .D wrote:
> I have for example these 4 bytes that I want to convert to int .
> hex:
> [3E 29 C3 39]
Hex is like decimal and like binary just a different view of the same 
number.

An integer has 32 bits and a hex digit has 4 bits. Therefore 8 hex 
digits are exactly 32 bis and you can simply concatenate the hex values 
in some order (lets assume left to right) and interpret it as an 
integer:
hex 3e29c339 = bin 111110001010011100001100111001 = dec 1042924345
But maybe the byte order is right to left the integer value is another 
one:
hex 39c3293e = bin 111001110000110010100100111110 = dec 969091390

If this answer doesn't help you, then maybe because information is 
missing: where does that hex number come from? Is it really a hex number 
or is it just a hex view of a binary number?

von Marthy .D (Guest)


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Lothar M. wrote:

> If this answer doesn't help you, then maybe because information is
> missing: where does that hex number come from? Is it really a hex number
> or is it just a hex view of a binary number?

No this is actually what I need thank you very much .
Another question : Is it possible to print a char in VHDL with the use 
of report ?

Maybe I didn't search well on the internet but I can't find it. I only 
know how to print an integer but not a char .

von Andreas S. (Company: Schweigstill IT) (schweigstill)


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Lothar M. wrote:
> hex 3e29c339 = bin 111110001010011100001100111001 = dec 1042924345
> But maybe the byte order is right to left the integer value is another
> one:
> hex 39c3293e = bin 111001110000110010100100111110 = dec 969091390

And on a PDP-11 and similar computers or processors with mixed endianess 
it would be:
hex 39c3293e = bin 001010010011111011100111000011

von Alexander S. (Company: Home) (alex_isr)


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Marthy .D wrote:
> Hello guys!
> How can we convert a 4 byte to int in VHDL ?

https://www.xilinx.com/support/answers/45213.html

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
entity conv_test is
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
b : out integer);
end conv_test;

architecture Behavioral of conv_test is

begin

b <= to_integer(signed(a));

end Behavioral;

 Regards Alex.


von Jörg W. (dl8dtl) (Moderator)


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Alexander S. wrote:

> Port ( a : in STD_LOGIC_VECTOR (7 downto 0);

So this is just one byte … the TO asked for concatenating 4 bytes.

Besides, the diagram on Lothar's web page covers more than just one 
direction:

http://www.lothar-miller.de/s9y/categories/16-Numeric_Std

(Description is in German, but ought to be obvious enough.)

von Alexander S. (Company: Home) (alex_isr)


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Alexander S. wrote:
> Marthy .D wrote:
>> Hello guys!
>> How can we convert a 4 byte to int in VHDL ?
>
> https://www.xilinx.com/support/answers/45213.html
>
 
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
 USE ieee.numeric_std.ALL;
 entity conv_test is
 Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
 b : out integer);
 end conv_test;
 
 architecture Behavioral of conv_test is
 
 begin
 
 b <= to_integer(signed(a));
 
 end Behavioral;
 
  Regards Alex.
 
 

 Attached ModelSim project of next VHDL design :
library ieee ;

use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity IntegerConvert  is
port
(
 ClockIn,
 nResetIn
                     : in std_logic;
 DataIn                                                                         -- Data for convert
                     : in std_logic_vector(15 downto 0);
 DataOut                                                                         -- Data Out
                     : out std_logic_vector(15 downto 0)
 );
end IntegerConvert;

architecture  ArchIntegerConvert of IntegerConvert is
signal Data : integer range 0 to 65535 := 0;
begin

 Name_Process:
process (ClockIn )
begin
 if(ClockIn'event and ClockIn = '1') then
  case nResetIn is
   when '0' =>
    Data     <= 0;
    DataOut <= (others => '0');
   when others =>
    Data     <= conv_integer(signed(DataIn));                -- Convert 4 Bytes to integer
    DataOut <= conv_std_logic_vector(Data,16);               -- Convert integer to 4 Bytes
  end case;
 end if;
end process  Name_Process;

end ArchIntegerConvert;


 Regards Alex.

 P.S.

conv_integer  conv_std_logic_vector in real design isn't need be 
clockable.
 It's only exapmle of usebility of convert in VHDL.

: Edited by User
von Lothar M. (lkmiller) (Moderator)


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Alexander S. wrote:
> It's only exapmle of usebility of convert in VHDL.
Do not use the old fashioned and obsolete synopsys arithmetic libs!
Use the  IEEE 1076.3 numeric_std instead.
And never ever use both togehter!

See that:
http://www.lothar-miller.de/s9y/categories/16-Numeric_Std
Its German, but Google translate helps out with a very readable 
translation:
https://translate.google.com/translate?hl=de&sl=de&tl=en&u=http%3A%2F%2Fwww.lothar-miller.de%2Fs9y%2Fcategories%2F16-Numeric_Std

von Jörg W. (dl8dtl) (Moderator)


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Besides:

Alexander S. wrote:
> DataOut <= conv_std_logic_vector(Data,16);               -- Convert
> integer to 4 Bytes

16 bits just makes for two bytes …

von Alexander S. (Company: Home) (alex_isr)


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Jörg W. wrote:
> Besides:
>
> Alexander S. wrote:
>> DataOut <= conv_std_logic_vector(Data,16);               -- Convert
>> integer to 4 Bytes
>
> 16 bits just makes for two bytes …

 You are righ :
library ieee ;

use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all;
-- use ieee.std_logic_unsigned.all;

entity IntegerConvert  is
port
(
 ClockIn,
 nResetIn
                     : in std_logic;
 DataIn                                                                         -- Data for convert
                     : in std_logic_vector(31 downto 0);
 DataOut                                                                         -- Data Out
                     : out std_logic_vector(31 downto 0)
 );
end IntegerConvert;

architecture  ArchIntegerConvert of IntegerConvert is
signal Data :  integer range 0 to 2147483647 := 0;
begin

 Name_Process:
process (ClockIn )
begin
 if(ClockIn'event and ClockIn = '1') then
  case nResetIn is
   when '0' =>
    Data     <= 0;
    DataOut <= (others => '0');
   when others =>
    Data     <= conv_integer(unsigned(DataIn));                            -- Convert 2 Bytes to integer
    DataOut <= conv_std_logic_vector(Data,32);                          -- Convert integer to 4 Bytes
  end case;
 end if;
end process  Name_Process;

end ArchIntegerConvert;


 Regards Alex.

 P.S.

A VHDL integer is defined from range -2147483648 to +2147483647.

https://www.edaboard.com/threads/vhdl-highest-possible-integer.247443/#:~:text=A%20VHDL%20integer%20is%20defined%20from%20range%20%2D2147483648%20to%20%2B2147483647.

: Edited by User
von Alexander S. (Company: Home) (alex_isr)


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Lothar M. wrote:
> Alexander S. wrote:
>> It's only exapmle of usebility of convert in VHDL.
> Do not use the old fashioned and obsolete synopsys arithmetic libs!

  convert in VHDL is not synthesizable virtual function for sintezis 
tools.
 Attached example is the only pipe line without arithmetic function.
 See attached picture and Vivado design
 Regards Alex.

: Edited by User
von Lothar M. (lkmiller) (Moderator)


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Marthy .D wrote:
> How can we convert a 4 byte to int in VHDL ?
Try it that way:
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
 USE ieee.numeric_std.ALL;

 entity conv_test is
 Port ( a,b,c,d : in STD_LOGIC_VECTOR (7 downto 0);
        x,y : out integer);
 end conv_test;
 
 architecture Behavioral of conv_test is
 begin
    x <= to_integer(signed(a&b&c&d)); -- two different byte orders
    y <= to_integer(signed(d&c&b&a)); 
 end Behavioral;


Alexander S. wrote:
> convert in VHDL is not synthesizable virtual function for sintezis tools.
Where did you find this strange statement?

> convert in VHDL is not synthesizable virtual function for sintezis tools.
You do not get the trick at all?
Of course: when you use the OLD and OBSOLETE std_logic_arith, then you 
MUST use the OLD and OBSOLETE std_logic_unsigned or the OLD and 
OBSOLETE std_logic_signed also.

All I said is: use the numeric_std without any of those OLD and 
OBSOLETE Synopsys math packages.

BTW: why the heck do you add latency (aka. flipflops) to a conversion?

: Edited by Moderator

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