VHDL Generic ADC SPI ControllerAttached ModelSim VHDL design of Generic ADC SPI Controller. Regards Alex.
Attached files:
Design after repair SpiSync Regards Alex.
Attached files:
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What do you mean with the word generic? Which ADCs are supported? Is the SPI used to configure ADCs like AD9650? What can be configured in your Code? Samplerate? Bits per Sample? Aquisition Time? Daisy Chaining of ADCs like AD7902? By now i wrote for most ADCs i used a individual HDL File to get the optimal timing. -gb- wrote: > What do you mean with the word generic? Generic : Number of bits (resolution). You also can select polarity of SpiClock and Spi Enable. You can define Spi Slock not more than 1/4 System Clock By addition clock. > Which ADCs are supported? One channel ADC without configuration commands. >Is the SPI used to configure ADCs like AD9650? No ! Currently I'm simulate other controller which can be used for multy channel ADC or ADC with configuration commands -gb- wrote: > to get the optimal timing. What's optimal timing for you ? Regards Alex. Alexander S. wrote: > Generic : Number of bits (resolution). > You also can select polarity of SpiClock and Spi Enable. > You can define Spi Slock not more than 1/4 System Clock By addition > clock. So this isn't a specialized SPI controller for ADC. >> Which ADCs are supported? > > One channel ADC without configuration commands. Great... this is the opposite of "generic". >>Is the SPI used to configure ADCs like AD9650? > > No ! So it can only be used only for a very small subset of ADCs. You are creating clock and synchronisation signals with both polarities which is quite a bad idea. If an external differential signal is needed it should be generated by the pin driver and not by the FPGA logic. Andreas S. wrote:
If an external differential signal is needed
You need configurate output of FPGA such as differential outpet or use
external hardware differential driver.
Regards Alex.
P.S.
You can use or SpiClock or not SpiClock according to definition of ADC.
Andreas S. wrote: > So it can only be used only for a very small subset of ADCs. One Channel without external configuration ADC. But it can be generated for 8,10,12,14,16 ... bits ADC with Spi Clock different (more slowly) from system clock according to your applbcation. It's not small subset of ADCs in the SC70 package. Regards Alex. Andreas S. wrote: > You are creating clock and synchronisation signals with both polarities > which is quite a bad idea. See Test Bench
For ADC I use only one of them according to ADC definifion. ReplyPlease log in before posting. |
