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Forum: FPGA, VHDL & Verilog vivado width mismatch error in synthesis


von Stefania M. (val_1010)


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Hi!
vivado gives me this error :
[Synth 8-690] width mismatch in assignment; target has 16 bits, source 
has 1 bits  for this line :  leds <= "0" & leds(length-1 to 1);
which is inserted in this contest :
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if leds = led_left then
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         direction <='1';
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         leds <= "0" & leds(length-1 to 1);
the leds vector and the main constants are defined in this way :
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kc: out STD_LOGIC_VECTOR(LENGTH-1 downto 0)
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length : integer :=16;
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constant kc_in : std_logic_vector(LENGTH-1 downto 0):=std_logic_vector(to_unsigned(2**kc'RIGHT,LENGTH));
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constant led_left : std_logic_vector(LENGTH-1 downto 0) :=
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std_logic_vector(to_unsigned(2**kc'LEFT,LENGTH));
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signal leds : STD_LOGIC_VECTOR(length-1 downto 0):=kc_in;
Where is the problem?
thank you very much

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


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Stefania M. wrote:
> leds <= "0" & leds(length-1 to 1);
Try that instead:
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  leds <= '0' & leds(length-1 to 1);

: Edited by Moderator
von Christoph Z. (christophz)


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Lothar M. wrote:
> Try that instead:  leds <= '0' & leds(length-1 to 1);

I think, it also needs to be "downto" instead of "to".

von Stefania M. (val_1010)


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I put downto and it worked!! thank you very much I really didn't notice!

: Edited by User

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