Hi!
vivado gives me this error :
[Synth 8-690] width mismatch in assignment; target has 16 bits, source
has 1 bits for this line : leds <= "0" & leds(length-1 to 1);
which is inserted in this contest :
1 | if leds = led_left then
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2 | direction <='1';
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3 | leds <= "0" & leds(length-1 to 1);
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the leds vector and the main constants are defined in this way :
1 | kc: out STD_LOGIC_VECTOR(LENGTH-1 downto 0)
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2 | length : integer :=16;
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3 |
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4 | constant kc_in : std_logic_vector(LENGTH-1 downto 0):=std_logic_vector(to_unsigned(2**kc'RIGHT,LENGTH));
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5 |
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6 | constant led_left : std_logic_vector(LENGTH-1 downto 0) :=
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7 | std_logic_vector(to_unsigned(2**kc'LEFT,LENGTH));
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8 | signal leds : STD_LOGIC_VECTOR(length-1 downto 0):=kc_in;
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Where is the problem?
thank you very much