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Forum: FPGA, VHDL & Verilog Determining signal


Determining signal
von Nimesh S. (Company: None) (nimesh13)

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I wish to monitor two signals and I wish to determine which of the two 
changed first and then do some work accordingly.
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 module tb(input sel1,

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                 input sel2);

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//Determine which of the two changed first

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if sel1 changed first :

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     //Do some work

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else :

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     //Do some Other work'

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endmodule

The above is a sample code. I have also attached a photo as an example. 
In the  photo, in the first instance sel1 changed first and the 2nd 
time, sel2 changed first, (NOTE : going from low to high is a change, 
according to the picture)
Can someone help me write a code which can help me to make out which of 
the signal changed first.
Thank you

  


  




  

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    Re: Determining signal
  


  

    

      von
      
        Darika (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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Nimesh S. wrote:
> The above is a sample code. I have also attached a photo as an example.

No, thats not code, it's just a useless snippet.
Also the module is useless, because it's missing any output,
Also a clock signal is missed, I would not start to design with latches 
because this is bad design practice.

  


  




  

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    Re: Determining signal
  


  

    

      von
      
        Nimesh S.
            (Company: None)
        (nimesh13)
        
      
      


      
    


    

      
    

    

    

  
  


  

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> Also the module is useless, because it's missing any output,

No, that code is not useless. There need not be any output in a module 
sometimes. I shall write a more specific code now.

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module tb(input sel1,

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          input sel2,

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          input hsel,

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          input data,

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          input addr);

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integer fd;

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initial 

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begin

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fd= $fopen(fd,"w");

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@(posedge hsel)

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// Determining which of the inputs changed first

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// if sel1 changed first

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  $fwrite(fd,data);

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else

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   $fwrite(fd,addr);

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$fclode(fd)

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end

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endmodule


The input is coming from a testing system which is put under 
verification.
Basically a design has been put under verification and it outputs some 
data which is being fed to this module and I need to record the output 
of the system under verification.

  


  




  

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    Re: Determining signal
  


  

    

      von
      
        Darika (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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It was not clear, that you are looking for a testbench simulation 
routine, which is not intended to be synthesized, because it was not 
mentioned in the task description.


For more details regarding evaluating time of events with verilog see:
http://www.testbench.in/SV_22_EVENTS.html

  


  




  

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