I wish to monitor two signals and I wish to determine which of the two changed first and then do some work accordingly.
module tb(input sel1, input sel2); //Determine which of the two changed first if sel1 changed first : //Do some work else : //Do some Other work' endmodule
The above is a sample code. I have also attached a photo as an example. In the photo, in the first instance sel1 changed first and the 2nd time, sel2 changed first, (NOTE : going from low to high is a change, according to the picture) Can someone help me write a code which can help me to make out which of the signal changed first. Thank you
Nimesh S. wrote: > The above is a sample code. I have also attached a photo as an example. No, thats not code, it's just a useless snippet. Also the module is useless, because it's missing any output, Also a clock signal is missed, I would not start to design with latches because this is bad design practice.
> Also the module is useless, because it's missing any output, No, that code is not useless. There need not be any output in a module sometimes. I shall write a more specific code now.
module tb(input sel1, input sel2, input hsel, input data, input addr); integer fd; initial begin fd= $fopen(fd,"w"); @(posedge hsel) // Determining which of the inputs changed first // if sel1 changed first $fwrite(fd,data); else $fwrite(fd,addr); $fclode(fd) end endmodule
The input is coming from a testing system which is put under verification. Basically a design has been put under verification and it outputs some data which is being fed to this module and I need to record the output of the system under verification.
It was not clear, that you are looking for a testbench simulation routine, which is not intended to be synthesized, because it was not mentioned in the task description. For more details regarding evaluating time of events with verilog see: http://www.testbench.in/SV_22_EVENTS.html