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VHDL error in project
von Fernando .S (Guest)

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So basically I'm trying to read a VHDL file with 3 colors (R,G,B)
with these formats :

image_width = 1666;
image_height = 1267;
Bit depth = 4;

I'm getting a fatal error at line 108 which is
(Sorry for the sudoku code ).
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--------------------------------------------------------------------------------------------------------------------------------------------------- ---------------------- 

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for row_i in 0 to image_height - 1 loop

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      -- Create a new row type in dynamic memory

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      row := new row_type(0 to image_width - 1);

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      for col_i in 0 to image_width - 1 loop

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     (=> THIS line) read(bmp_file, char);

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---------------------------------------------------------------------------

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library ieee;

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use ieee.std_logic_1164.all;

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use ieee.numeric_std.all;

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use std.textio.all;

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use std.env.finish;

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entity read_bmp_tb is

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end read_bmp_tb;

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architecture sim of read_bmp_tb is

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  type header_type  is array (0 to 117) of character;

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  type pixel_type is record

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    red : std_logic_vector(7 downto 0);

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    green : std_logic_vector(7 downto 0);

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    blue : std_logic_vector(7 downto 0);

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  end record;

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  type row_type is array (integer range <>) of pixel_type;

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  type row_pointer is access row_type;

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  type image_type is array (integer range <>) of row_pointer;

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  type image_pointer is access image_type;

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  -- DUT signals

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  signal r_in : std_logic_vector(7 downto 0);

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  signal g_in : std_logic_vector(7 downto 0);

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  signal b_in : std_logic_vector(7 downto 0);

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  signal r_out : std_logic_vector(7 downto 0);

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  signal g_out : std_logic_vector(7 downto 0);

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  signal b_out : std_logic_vector(7 downto 0);

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begin

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  DUT :entity work.grayscale(rtl)

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  port map (

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    r_in => r_in,

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    g_in => g_in,

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    b_in => b_in,

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    r_out => r_out,

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    g_out => g_out,

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    b_out => b_out

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  );

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  process

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    type char_file is file of character;

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    file bmp_file : char_file open read_mode is "Before.bmp";

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    file out_file : char_file open write_mode is "After.bmp";

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    variable header : header_type;

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    variable image_width : integer;

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    variable image_height : integer;

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    variable row : row_pointer;

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    variable image : image_pointer;

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    variable padding : integer;

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    variable char : character;

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  begin

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    -- Read entire header

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    for i in header_type'range loop

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      read(bmp_file, header(i));

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    end loop;  

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    image_width := 1666;

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    image_height := 1267;

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    -- Number of bytes needed to pad each row to 32 bits

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    padding := (4 - image_width*3 mod 4) mod 4;

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    report "padding: " & integer'image(padding);

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    -- Create a new image type in dynamic memory

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    image := new image_type(0 to image_height - 1);

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    for row_i in 0 to image_height - 1 loop

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      -- Create a new row type in dynamic memory

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      row := new row_type(0 to image_width - 1);

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      for col_i in 0 to image_width - 1 loop

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-------------------------------------------------------------------------------------------------------------------------------------------------------------

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        -- Read blue pixel

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 --------------------------------------------- --------------------------------------------- ---------------------------------------------   

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        read(bmp_file, char);//Error starts from here 

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        row(col_i).blue :=

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          std_logic_vector(to_unsigned(character'pos(char), 8));

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        -- Read green pixel

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        read(bmp_file, char);

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        row(col_i).green :=

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          std_logic_vector(to_unsigned(character'pos(char), 8));

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        -- Read red pixel

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        read(bmp_file, char);

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        row(col_i).red :=

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          std_logic_vector(to_unsigned(character'pos(char), 8));

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      end loop;

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      -- Read and discard padding

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      for i in 1 to padding loop

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        read(bmp_file, char);

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      end loop;

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      -- Assign the row pointer to the image vector of rows

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      image(row_i) := row;

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    end loop;

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    -- DUT test

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    for row_i in 0 to image_height - 1 loop

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      row := image(row_i);

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      for col_i in 0 to image_width - 1 loop

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        r_in <= row(col_i).red;

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        g_in <= row(col_i).green;

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        b_in <= row(col_i).blue;

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        wait for 10 ns;

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        row(col_i).red := r_out;

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        row(col_i).green := g_out;

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        row(col_i).blue := b_out;

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      end loop;

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    end loop;

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    -- Write header to output file

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    for i in header_type'range loop

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      write(out_file, header(i));

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    end loop;

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    for row_i in 0 to image_height - 1 loop

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      row := image(row_i);

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      for col_i in 0 to image_width - 1 loop

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        -- Write blue pixel

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        write(out_file,

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          character'val(to_integer(unsigned(row(col_i).blue))));

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        -- Write green pixel

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        write(out_file,

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          character'val(to_integer(unsigned(row(col_i).green))));

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        -- Write red pixel

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        write(out_file,

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          character'val(to_integer(unsigned(row(col_i).red))));

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      end loop;

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      deallocate(row);

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      -- Write padding

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      for i in 1 to padding loop

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        write(out_file, character'val(0));

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      end loop;

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    end loop;

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    deallocate(image);

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    file_close(bmp_file);

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    file_close(out_file);

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    report "Simulation done. Check ""out.bmp"" image.";

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    finish;

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  end process;

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end architecture;

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----------------------------------------------------------------------------------------------------------------------------------------

I appreciate any help on the code thanks

  


  



  

  
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    Re: VHDL error in project
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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Fernando .S wrote:
1
        read(bmp_file, char);    // Error starts from here --> is that really the problem?

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        row(col_i).blue := std_logic_vector(to_unsigned(character'pos(char), 8));  -->  or is it here?

Did you single step through the source code?


> I appreciate any help
Pls use the [vhdl] tags to wrap your code. See "Formatting options" a 
few lines over each text input box.

  


  



  

  
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    Re: VHDL error in project
  


  

    

      von
      
        Fernando .S (Guest)
      
      


      
    


    

      
    

    

    

      

      

      Attached files:



        
    

  
  


  

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I tried a smaller code to check if read function is working correctly or 
not .

When I run the simulation I keep getting this :

# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading std.env(body)
# Loading work.readbmp(reading)

  


  




  

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    Re: VHDL error in project
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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Fernando .S wrote:
> When I run the simulation I keep getting this :
Nothing else? On which simulator? Can you do single stepping on that 
simulator?

> vhdl.png
> I tried a smaller code
Pls. post that CODE in ASCII as a *.vhd odr a *.vhdl file. Its simply 
impossible to copy&past some test out of a picture.

Or do it as I already wrote:
> Pls use the [vhdl] tags to wrap your code. See "Formatting options" a
> few lines over each text input box.

  


  




  

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    Re: VHDL error in project
  


  

    

      von
      
        Fernando .S (Guest)
      
      


      
    


    

      
    

    

    

      

      

      Attached files:


      

    

  
  


  

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Yes nothing else showed up .

I tried to wait for half an hour thinking that the data that I wrote may 
too big but it's actually not .

What do you mean by single stepping on the simulator ? I don't know 
that.

It just keeps showing these messages
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading std.env(body)
# Loading work.readbmp(reading)

  


  




  

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    Re: VHDL error in project
  


  

    

      von
      
        Fernando .S (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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I'm Using modelsim

  


  




  

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