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Forum: FPGA, VHDL & Verilog VHDL error in project


von Fernando .S (Guest)


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So basically I'm trying to read a VHDL file with 3 colors (R,G,B)
with these formats :

image_width = 1666;
image_height = 1267;
Bit depth = 4;

I'm getting a fatal error at line 108 which is
(Sorry for the sudoku code ).
--------------------------------------------------------------------------------------------------------------------------------------------------- ---------------------- 


for row_i in 0 to image_height - 1 loop

      -- Create a new row type in dynamic memory
      row := new row_type(0 to image_width - 1);

      for col_i in 0 to image_width - 1 loop
     (=> THIS line) read(bmp_file, char);

---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use std.textio.all;
use std.env.finish;

entity read_bmp_tb is
end read_bmp_tb;

architecture sim of read_bmp_tb is

  type header_type  is array (0 to 117) of character;

  type pixel_type is record
    red : std_logic_vector(7 downto 0);
    green : std_logic_vector(7 downto 0);
    blue : std_logic_vector(7 downto 0);
  end record;

  type row_type is array (integer range <>) of pixel_type;
  type row_pointer is access row_type;
  type image_type is array (integer range <>) of row_pointer;
  type image_pointer is access image_type;

  -- DUT signals
  signal r_in : std_logic_vector(7 downto 0);
  signal g_in : std_logic_vector(7 downto 0);
  signal b_in : std_logic_vector(7 downto 0);

  signal r_out : std_logic_vector(7 downto 0);
  signal g_out : std_logic_vector(7 downto 0);
  signal b_out : std_logic_vector(7 downto 0);

begin

  DUT :entity work.grayscale(rtl)
  port map (
    r_in => r_in,
    g_in => g_in,
    b_in => b_in,

    r_out => r_out,
    g_out => g_out,
    b_out => b_out
  );

  process
    type char_file is file of character;
    file bmp_file : char_file open read_mode is "Before.bmp";
    file out_file : char_file open write_mode is "After.bmp";
    variable header : header_type;
    variable image_width : integer;
    variable image_height : integer;
    variable row : row_pointer;
    variable image : image_pointer;
    variable padding : integer;
    variable char : character;
  begin

    -- Read entire header
    for i in header_type'range loop
      read(bmp_file, header(i));
    end loop;  

    image_width := 1666;

    image_height := 1267;

    -- Number of bytes needed to pad each row to 32 bits
    padding := (4 - image_width*3 mod 4) mod 4;
    report "padding: " & integer'image(padding);

    -- Create a new image type in dynamic memory
    image := new image_type(0 to image_height - 1);

    for row_i in 0 to image_height - 1 loop

      -- Create a new row type in dynamic memory
      row := new row_type(0 to image_width - 1);

      for col_i in 0 to image_width - 1 loop
-------------------------------------------------------------------------------------------------------------------------------------------------------------
        -- Read blue pixel
 --------------------------------------------- --------------------------------------------- ---------------------------------------------   
        read(bmp_file, char);//Error starts from here 
        row(col_i).blue :=
          std_logic_vector(to_unsigned(character'pos(char), 8));

        -- Read green pixel
        read(bmp_file, char);
        row(col_i).green :=
          std_logic_vector(to_unsigned(character'pos(char), 8));

        -- Read red pixel
        read(bmp_file, char);
        row(col_i).red :=
          std_logic_vector(to_unsigned(character'pos(char), 8));

      end loop;

      -- Read and discard padding
      for i in 1 to padding loop
        read(bmp_file, char);
      end loop;

      -- Assign the row pointer to the image vector of rows
      image(row_i) := row;

    end loop;

    -- DUT test
    for row_i in 0 to image_height - 1 loop
      row := image(row_i);

      for col_i in 0 to image_width - 1 loop

        r_in <= row(col_i).red;
        g_in <= row(col_i).green;
        b_in <= row(col_i).blue;
        wait for 10 ns;

        row(col_i).red := r_out;
        row(col_i).green := g_out;
        row(col_i).blue := b_out;

      end loop;
    end loop;

    -- Write header to output file
    for i in header_type'range loop
      write(out_file, header(i));
    end loop;

    for row_i in 0 to image_height - 1 loop
      row := image(row_i);

      for col_i in 0 to image_width - 1 loop

        -- Write blue pixel
        write(out_file,
          character'val(to_integer(unsigned(row(col_i).blue))));

        -- Write green pixel
        write(out_file,
          character'val(to_integer(unsigned(row(col_i).green))));

        -- Write red pixel
        write(out_file,
          character'val(to_integer(unsigned(row(col_i).red))));

      end loop;

      deallocate(row);

      -- Write padding
      for i in 1 to padding loop
        write(out_file, character'val(0));
      end loop;

    end loop;

    deallocate(image);

    file_close(bmp_file);
    file_close(out_file);

    report "Simulation done. Check ""out.bmp"" image.";
    finish;
  end process;

end architecture;

----------------------------------------------------------------------------------------------------------------------------------------
I appreciate any help on the code thanks

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


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Fernando .S wrote:
        read(bmp_file, char);    // Error starts from here --> is that really the problem?

        row(col_i).blue := std_logic_vector(to_unsigned(character'pos(char), 8));  -->  or is it here?
Did you single step through the source code?


> I appreciate any help
Pls use the [vhdl] tags to wrap your code. See "Formatting options" a 
few lines over each text input box.

: Edited by Moderator
von Fernando .S (Guest)


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I tried a smaller code to check if read function is working correctly or 
not .

When I run the simulation I keep getting this :

# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading std.env(body)
# Loading work.readbmp(reading)

von Lothar M. (lkmiller) (Moderator)


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Fernando .S wrote:
> When I run the simulation I keep getting this :
Nothing else? On which simulator? Can you do single stepping on that 
simulator?

> vhdl.png
> I tried a smaller code
Pls. post that CODE in ASCII as a *.vhd odr a *.vhdl file. Its simply 
impossible to copy&past some test out of a picture.

Or do it as I already wrote:
> Pls use the [vhdl] tags to wrap your code. See "Formatting options" a
> few lines over each text input box.

von Fernando .S (Guest)


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Yes nothing else showed up .

I tried to wait for half an hour thinking that the data that I wrote may 
too big but it's actually not .

What do you mean by single stepping on the simulator ? I don't know 
that.

It just keeps showing these messages
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading std.env(body)
# Loading work.readbmp(reading)

von Fernando .S (Guest)


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I'm Using modelsim

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