VHDL Generic Spi Transmit by System Clock SpeedAttached ModelSim VHDL design of Generic Spi Transmit System Clock Speed OutPut. Regards Alex
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Alexander S. wrote: > Spi Transmit System Clock Speed OutPut What the heck is a "Spi Transmit System Clock Speed OutPut"? What can we see on the screenshot? And whats the problem with it?
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Lothar M. wrote: > What the heck that's exactly what comes to my mind... Lothar M. wrote: > Alexander S. wrote: >> Spi Transmit System Clock Speed OutPut > What the heck is a "Spi Transmit System Clock Speed OutPut"? What can > we see on the screenshot? And whats the problem with it? SPI clcock and systev clock ie the same clock. It's max. SPI clock. Regards Alex. Lothar M. wrote:
And whats the problem with it?
I want to know if you (with your expirience) or anybody see problem
such you saw in my other designs ?
Regards Alex.
Alexander S. wrote: > I want to know if you or anybody see problem such you saw in my other > designs ? Select one out of two: 1. I don't open zipped files. (because of viruses etc.) 2. I can't open zipped files. (because I'm on a mobile device) > problem such you saw in my other designs ? I opened some of the first zip files you posted. Since then see 1. BTW: Why should I (or anyone else) discuss your code, when you post some 12 year old designs without any comment or question or having an actual problem? Lothar M. wrote: > Why should I (or anyone else) discuss your code Nobody owes anything to anyone. Only if you are interested and you want. Regards alex. Lothar M. wrote: without ... having an actual > problem? I've experience looking for problem of design after 10 years working in the device. I want see problems more before . Regards Alex. Reply |
