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Forum: FPGA, VHDL & Verilog VHDL Generic Bus I/O MUX


von Alexander S. (Company: Home) (alex_isr)


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Attached ModelSim VHDL design of Generic Bus I/O MUX.

Regards Alex.

von Griz Lee (Guest)


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You published pretty lot of files today, but a closer look shows, most 
of them are simple and some even faulty and crappy. This is not standard 
code quality.

von Alexander S. (Company: Home) (alex_isr)


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Griz Lee wrote:
> You published pretty lot of files today, but a closer look shows,
>most of them

>are simple

 Yes, these are "stones" for my large projects.

>and some even faulty and crappy. This is not standard code quality.

 You can explain that to all and I'll try to repair it ... I will say 
you thanx.

 Regards alex.

: Edited by User
von Lothar M. (lkmiller) (Moderator)


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Alexander S. wrote:
> Attached ModelSim VHDL design of Generic Bus I/O MUX.
I don't understand what the whole thing is good for. A tristate buffer 
usually needs not more than two lines.

A few words to that code:
InOutProcess:
process (ClockIn,nEnableIn)
begin
 if nEnableIn = '0' then
  DataIO      <= DataIn;
 else
  DataIO     <= (others => 'Z');
 end if;
 if ClockIn'event and ClockIn = '1'then
  case nResetIn is
  when '0' => DataOutValid <= '0'; -- Data for trnsport from DataIO to FPGA valid
              DataOut <= (others => '0');
  when others =>
              DataOutValid <= nEnableIn; -- Data for trnsport from DataIO to FPGA valid
              DataOut   <= DataIO;
  end case;
 end if;
end process InOutProcess;
Never ever use combinatorial and synchronous descriptions in the same 
process!
Additionally the simulation will be wrong due to the missing "DataIn" in 
the sensitivity list.

: Edited by Moderator
von Alexander S. (Company: Home) (alex_isr)


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Lothar M. wrote:
> Never ever use combinatorial and synchronous descriptions in the same
> process!

 You are right :
library ieee;
use ieee.std_logic_1164.all;

entity InOutGen is
GENERIC (DataRange  : integer);
port
 (
  ClockIn,                                                                      -- General Clock
  nResetIn,                                                                     -- General Reset active low
  nEnableIn      : in    std_logic;                                              -- Active 0 for read from FPGA
  DataIn         : in    std_logic_vector(DataRange downto 0);                   -- Data for trnsport from FPGA to DataIO
  DataOutValid  : out   std_logic;                                               -- Data for trnsport from DataIO to FPGA valid
  DataOut        : out   std_logic_vector(DataRange downto 0);                   -- Data for trnsport from DataIO to FPGA
  DataIO         : inout std_logic_vector(DataRange downto 0)                    -- External Data Bus
 );
end InOutGen;

architecture ArchInOutGen of InOutGen is

begin

OutProcess:
process (nEnableIn)
begin
 if nEnableIn = '0' then
  DataIO      <= DataIn;
 else
  DataIO       <= (others => 'Z');
 end if;
end process OutProcess;

InProcess:
process (ClockIn)
begin
 if ClockIn'event and ClockIn = '1'then
  case nResetIn is
   when '0' =>
    DataOutValid <='0';                                                         -- Data for trnsport from DataIO to FPGA valid
    DataOut   <= (others => '0');
    when others =>
    DataOutValid   <= nEnableIn;                                                 -- Data for trnsport from DataIO to FPGA valid
    DataOut       <= DataIO;
  end case;
 end if;
end process InProcess;


 Thank you for good cooperation.

 Regards Alex.

von Lothar M. (lkmiller) (Moderator)


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Alexander S. wrote:
 OutProcess:
 process (nEnableIn)
 begin
  if nEnableIn = '0' then
   DataIO      <= DataIn;
  else
   DataIO       <= (others => 'Z');
  end if;
 end process OutProcess;
As already said: the simulation doesn't fit reality due to an incomplete 
sensitivity list. DataIn is missing.

All in all this process is just bloating code. It can be replaced by 1 
concurrent line of code:
 DataIO <= DataIn when nEnableIn='0' else (others => 'Z');

: Edited by Moderator
von Alexander S. (Company: Home) (alex_isr)


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Lothar M. wrote:

> As already said: the simulation doesn't fit reality due to an incomplete
> sensitivity list. DataIn is missing.

 Thanx.
 
OutProcess:
process (nEnableIn,DataIn)
begin
 if nEnableIn = '0' then
  DataIO      <= DataIn;
 else
  DataIO       <= (others => 'Z');
 end if;
end process OutProcess;

 Usually, I use synchronous only process which have only clock in the 
sensitivity list.

 Regards Alex.

: Edited by Moderator

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