VHDL Generic Bus I/O MUX

Alexander S. (alex_isr) OP (Company: Home) 2020-06-12 18:51 #6300566

Rate this post

•	▲ useful ▼ not useful

Attached ModelSim VHDL design of Generic Bus I/O MUX.

Regards Alex.

Attached files:

InOutGen.zip (83.7 KB)

InOutGen.PNG (51 KB)

Reply Quote Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Report post

Griz Lee Guest 2020-06-14 17:36 #6303120

Rate this post

•	▲ useful ▼ not useful

You published pretty lot of files today, but a closer look shows, most 
of them are simple and some even faulty and crappy. This is not standard 
code quality.

Reply Quote Edit Delete Report post

Alexander S. (alex_isr) OP (Company: Home) 2020-06-15 08:28 #6303884

Rate this post

•	▲ useful ▼ not useful

Griz Lee wrote:
> You published pretty lot of files today, but a closer look shows,
>most of them

>are simple

 Yes, these are "stones" for my large projects.

>and some even faulty and crappy. This is not standard code quality.

 You can explain that to all and I'll try to repair it ... I will say 
you thanx.

 Regards alex.

Reply Quote Edit Delete Report post

Lothar M. (lkmiller) Moderator (Company: Titel) 2020-06-15 09:36 #6303958

Rate this post

•	▲ useful ▼ not useful

Alexander S. wrote:
> Attached ModelSim VHDL design of Generic Bus I/O MUX.
I don't understand what the whole thing is good for. A tristate buffer 
usually needs not more than two lines.

A few words to that code:

InOutProcess:
process (ClockIn,nEnableIn)
 if nEnableIn = '0' then
  DataIO      <= DataIn;
  DataIO     <= (others => 'Z');
 if ClockIn'event and ClockIn = '1'then
  case nResetIn is
  when '0' => DataOutValid <= '0'; -- Data for trnsport from DataIO to FPGA valid
              DataOut <= (others => '0');
  when others =>
              DataOutValid <= nEnableIn; -- Data for trnsport from DataIO to FPGA valid
              DataOut   <= DataIO;
  end case;
 end if;
end process InOutProcess;

Never ever use combinatorial and synchronous descriptions in the same 
process!
Additionally the simulation will be wrong due to the missing "DataIn" in 
the sensitivity list.

Reply Quote Edit Delete Report post

Alexander S. (alex_isr) OP (Company: Home) 2020-06-15 11:23 #6304082

Rate this post

•	▲ useful ▼ not useful

Lothar M. wrote:
> Never ever use combinatorial and synchronous descriptions in the same
> process!

 You are right :

library ieee;
use ieee.std_logic_1164.all;
entity InOutGen is
GENERIC (DataRange  : integer);
  ClockIn,                                                                      -- General Clock
  nResetIn,                                                                     -- General Reset active low
  nEnableIn      : in    std_logic;                                              -- Active 0 for read from FPGA
  DataIn         : in    std_logic_vector(DataRange downto 0);                   -- Data for trnsport from FPGA to DataIO
  DataOutValid  : out   std_logic;                                               -- Data for trnsport from DataIO to FPGA valid
  DataOut        : out   std_logic_vector(DataRange downto 0);                   -- Data for trnsport from DataIO to FPGA
  DataIO         : inout std_logic_vector(DataRange downto 0)                    -- External Data Bus
end InOutGen;
architecture ArchInOutGen of InOutGen is
OutProcess:
process (nEnableIn)
 if nEnableIn = '0' then
  DataIO      <= DataIn;
  DataIO       <= (others => 'Z');
 end if;
end process OutProcess;
InProcess:
process (ClockIn)
 if ClockIn'event and ClockIn = '1'then
  case nResetIn is
   when '0' =>
    DataOutValid <='0';                                                         -- Data for trnsport from DataIO to FPGA valid
    DataOut   <= (others => '0');
    when others =>
    DataOutValid   <= nEnableIn;                                                 -- Data for trnsport from DataIO to FPGA valid
    DataOut       <= DataIO;
  end case;
 end if;
end process InProcess;


 Thank you for good cooperation.

 Regards Alex.

Attached files:

InOutGen_150620.zip (85.4 KB)

Reply Quote Edit Delete Report post

Lothar M. (lkmiller) Moderator (Company: Titel) 2020-06-15 11:30 #6304100

Rate this post

•	▲ useful ▼ not useful

Alexander S. wrote:

 OutProcess:
 process (nEnableIn)
  if nEnableIn = '0' then
   DataIO      <= DataIn;
   DataIO       <= (others => 'Z');
  end if;
 end process OutProcess;

As already said: the simulation doesn't fit reality due to an incomplete 
sensitivity list. DataIn is missing.

All in all this process is just bloating code. It can be replaced by 1 
concurrent line of code:

 DataIO <= DataIn when nEnableIn='0' else (others => 'Z');

Reply Quote Edit Delete Report post

Alexander S. (alex_isr) OP (Company: Home) 2020-06-15 11:49 #6304120

Rate this post

•	▲ useful ▼ not useful

Lothar M. wrote:

> As already said: the simulation doesn't fit reality due to an incomplete
> sensitivity list. DataIn is missing.

 Thanx.

OutProcess:
process (nEnableIn,DataIn)
 if nEnableIn = '0' then
  DataIO      <= DataIn;
  DataIO       <= (others => 'Z');
end process OutProcess;


 Usually, I use synchronous only process which have only clock in the 
sensitivity list.

 Regards Alex.

Attached files:

InOutGen_01_150620.zip (85.5 KB)

Reply Quote Edit Delete Report post