VHDL Generic Bus I/O MUX

Lothar M. Moderator (Company: Titel) #6303958
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Alexander S. wrote:
> Attached ModelSim VHDL design of Generic Bus I/O MUX.
I don't understand what the whole thing is good for. A tristate buffer 
usually needs not more than two lines.

A few words to that code:
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InOutProcess:

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process (ClockIn,nEnableIn)

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begin

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 if nEnableIn = '0' then

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  DataIO      <= DataIn;

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 else

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  DataIO     <= (others => 'Z');

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 end if;

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 if ClockIn'event and ClockIn = '1'then

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  case nResetIn is

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  when '0' => DataOutValid <= '0'; -- Data for trnsport from DataIO to FPGA valid

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              DataOut <= (others => '0');

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  when others =>

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              DataOutValid <= nEnableIn; -- Data for trnsport from DataIO to FPGA valid

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              DataOut   <= DataIO;

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  end case;

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 end if;

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end process InOutProcess;

Never ever use combinatorial and synchronous descriptions in the same 
process!
Additionally the simulation will be wrong due to the missing "DataIn" in 
the sensitivity list.
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Alexander S. OP (Company: Home) #6304082
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Lothar M. wrote:
> Never ever use combinatorial and synchronous descriptions in the same
> process!

 You are right :

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library ieee;

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use ieee.std_logic_1164.all;

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entity InOutGen is

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GENERIC (DataRange  : integer);

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port

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 (

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  ClockIn,                                                                      -- General Clock

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  nResetIn,                                                                     -- General Reset active low

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  nEnableIn      : in    std_logic;                                              -- Active 0 for read from FPGA

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  DataIn         : in    std_logic_vector(DataRange downto 0);                   -- Data for trnsport from FPGA to DataIO

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  DataOutValid  : out   std_logic;                                               -- Data for trnsport from DataIO to FPGA valid

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  DataOut        : out   std_logic_vector(DataRange downto 0);                   -- Data for trnsport from DataIO to FPGA

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  DataIO         : inout std_logic_vector(DataRange downto 0)                    -- External Data Bus

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 );

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end InOutGen;

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architecture ArchInOutGen of InOutGen is

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begin

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OutProcess:

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process (nEnableIn)

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begin

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 if nEnableIn = '0' then

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  DataIO      <= DataIn;

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 else

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  DataIO       <= (others => 'Z');

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 end if;

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end process OutProcess;

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InProcess:

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process (ClockIn)

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begin

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 if ClockIn'event and ClockIn = '1'then

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  case nResetIn is

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   when '0' =>

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    DataOutValid <='0';                                                         -- Data for trnsport from DataIO to FPGA valid

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    DataOut   <= (others => '0');

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    when others =>

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    DataOutValid   <= nEnableIn;                                                 -- Data for trnsport from DataIO to FPGA valid

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    DataOut       <= DataIO;

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  end case;

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 end if;

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end process InProcess;


 Thank you for good cooperation.

 Regards Alex.
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Lothar M. Moderator (Company: Titel) #6304100
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Alexander S. wrote:
1
 OutProcess:

2
 process (nEnableIn)

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 begin

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  if nEnableIn = '0' then

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   DataIO      <= DataIn;

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  else

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   DataIO       <= (others => 'Z');

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  end if;

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 end process OutProcess;

As already said: the simulation doesn't fit reality due to an incomplete 
sensitivity list. DataIn is missing.

All in all this process is just bloating code. It can be replaced by 1 
concurrent line of code:
1
 DataIO <= DataIn when nEnableIn='0' else (others => 'Z');
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Alexander S. OP (Company: Home) #6304120
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Lothar M. wrote:

> As already said: the simulation doesn't fit reality due to an incomplete
> sensitivity list. DataIn is missing.

 Thanx.

1
 

2
OutProcess:

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process (nEnableIn,DataIn)

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begin

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 if nEnableIn = '0' then

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  DataIO      <= DataIn;

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 else

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  DataIO       <= (others => 'Z');

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 end if;

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end process OutProcess;


 Usually, I use synchronous only process which have only clock in the 
sensitivity list.

 Regards Alex.
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