VHDL Generic Counter with Clocked Rise OutPut

Alexander S. wrote:
> design of Generic Counter with Clocked Rise OutPut.
All in all I see a very laborious way to generate a clock enable. Whats 
the advantage prior to a simple counter?

One word to this:

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GENERIC (DivideRange  : integer);

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:

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signal ClockDivider, DividerFactor : integer range 0 to DivideRange;

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:

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begin

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:

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       DividerFactor <= DivideRange - 1;

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       ClockDivider <= ClockDivider + 1 mod DividerFactor;

As "mod" implements a divider, this design will lead to extensive logic 
with some values for "DivideRange". Because only values in (2**x+1) will 
be easily synthesizable.

Lothar M. wrote:
> As "mod" implements a divider, this design will lead to extensive logic
> with some values for "DivideRange". Because only values in (2**x+1) will


> be easily synthesizable.

-----------
https://www.ics.uci.edu/~jmoorkan/vhdlref/vhdl_golden_reference_guide.pdf

The
VHDL
Golden
Reference
Guide

Page 80 :

Operator

Synthesis

 The operators / mod ... ** are not synthesizable

 Regards Alex.

Alexander S. wrote:
> The operators / mod ... ** are not synthesizable
Of  course x/(2**n) is synthesizable, because it's only some rewiring.
E.g. for x/4 just the lowest 2 bits are skipped.

And when a division is synthesizable, then "mod" is also, because that's 
only to ignore the upper bits.

> Alexander S. wrote:
>> The operators / mod ... ** are not synthesizable

 So, synthesis tools is ignore mod statement and really no problem in 
the hardware ?

 Regards Alex.