Alexander S. wrote:
> with synchronous output.
What I say is: there is no need for a synchronous output when the
ongoing stages are synchronous. Syncing just adds latency, becasuse
syncing adds flipflops.
Alexander S. wrote:
> but my design
1 | PipeLine:
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2 | process (ClockIn)
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3 | begin
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4 | if(ClockIn'event and ClockIn = '1') then
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5 | case nResetIn is
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6 | when '0' =>
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7 | InputSignalF <= '0';
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8 | InputSignalFf <= '0';
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9 | nInputSignalF <= '1';
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10 | nInputSignalFf <= '1';
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11 | when others =>
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12 | InputSignalF <= InputSignal ;
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13 | InputSignalFf <= InputSignalf ;
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14 | nInputSignalF <= not InputSignal ;
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15 | nInputSignalFf <= nInputSignalF ;
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16 | end case;
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17 | end if;
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18 | end process PipeLine;
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19 |
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20 | OutProcess:
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21 | process(nClockIn)
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22 | begin
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23 | if (nClockIn'event and nClockIn = '1') then
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24 | case nResetIn is
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25 | when '0' =>
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26 | RiseOutput <= '0';
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27 | FallOutput <= '0';
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28 | when others =>
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29 | RiseOutput <= InputSignalF and ( not InputSignalFf );
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30 | FallOutput <= nInputSignalF and ( not nInputSignalFf );
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31 | end case;
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32 | end if;
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33 | end process OutProcess;
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Your design has 2 shift register of each 2 bits length. One is for the
direct input signal and one for the inverted.
Your code does therefore the very same like that here:
1 | signal srp, srn : std_logic_vector (1 downto 0);
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2 |
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3 | process (nClockIn) begin
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4 | if rising_edge(nClockIn) then
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5 | -- sync in input signal
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6 | srp <= srp(0) & InputSignal;
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7 | srn <= srn(0) & (not InputSignal);
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8 |
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9 | -- check for edges
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10 | FallOutput <= '1' when srp = "10" else '0';
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11 | RiseOutput <= '1' when srn = "10" else '0';
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12 | end if;
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13 | end process;
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And it can be shortened to this:
1 | signal sr : std_logic_vector (1 downto 0);
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2 |
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3 | process (nClockIn) begin
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4 | if rising_edge(nClockIn) then
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5 | -- sync in input signal
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6 | sr <= sr(0) & InputSignal;
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7 |
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8 | -- check for edges
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9 | FallOutput <= '1' when sr = "10" else '0';
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10 | RiseOutput <= '1' when sr = "01" else '0';
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11 | end if;
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12 | end process;
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> Excuse me
No problem. You do it your way, I do it mine. And be sure: I learn from
your code...
