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Forum: FPGA, VHDL & Verilog VHDL Rise/Fall Detector


von Alexander S. (Company: Home) (alex_isr)


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Attached ModelSim VHDL design of signal Rise/Fall Detector.

Regards Alex.

: Edited by User
von Lothar M. (lkmiller) (Moderator)


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To keep things short I use shift a 3 bit shift register:
-- sync in input signal
sr <= sr(1 downto 0) & InputSignal when rising_edge(clk);

-- check for edges
FallOutput <= '1' when sr(2 downto 1) = "10" else '0';
RiseOutput <= '1' when sr(2 downto 1) = "01" else '0';
I do not use a reset for such simple tasks, because I can't see no 
benefit.

von Alexander S. (Company: Home) (alex_isr)


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What max. delay you have ?
How many clocks ?
 Your outputs does not clocked !!!

: Edited by User
von Lothar M. (lkmiller) (Moderator)


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Alexander S. wrote:
> What max. delay you have ?
On the output one clock less than your design (your design has 
unnecessary latency).

> How many clocks ?
Ideally only one clock in the whole design.

> Your outputs does not clocked !!!
Yes, because
- it's not necessary when the whole rest of the design is clocked
- there's no additional latency due to unnecessary flipflops in my 
design

BTW: your question are very entry level. You simply can answer them 
yourself. Just implement my three lines in your code.

: Edited by Moderator
von Alexander S. (Company: Home) (alex_isr)


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Lothar M. wrote:
>> How many clocks ?
> Ideally only one clock in the whole design.

Excuse me, but my design have delay from 0.5 to 1.5 clocks with 
synchronous output.
 Regards Alex.

von Lothar M. (lkmiller) (Moderator)


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Alexander S. wrote:
> with synchronous output.
What I say is: there is no need for a synchronous output when the 
ongoing stages are synchronous. Syncing just adds latency, becasuse 
syncing adds flipflops.

Alexander S. wrote:
> but my design
PipeLine:
process  (ClockIn)
begin
if(ClockIn'event and ClockIn = '1') then
 case nResetIn is
  when '0' =>
   InputSignalF      <= '0';
   InputSignalFf     <= '0';
   nInputSignalF    <= '1';
   nInputSignalFf   <= '1';
  when others =>
   InputSignalF     <= InputSignal  ;
   InputSignalFf     <= InputSignalf ;
   nInputSignalF     <= not InputSignal  ;
   nInputSignalFf    <= nInputSignalF ;
 end case;
end if;
end process PipeLine;

OutProcess:
process(nClockIn)
begin
if (nClockIn'event and nClockIn = '1') then
 case nResetIn is
  when '0' =>
   RiseOutput  <= '0';
   FallOutput  <= '0';
  when others =>
   RiseOutput   <=  InputSignalF and ( not  InputSignalFf );
   FallOutput   <= nInputSignalF and ( not nInputSignalFf );
 end case;
end if;
end process OutProcess;
Your design has 2 shift register of each 2 bits length. One is for the 
direct input signal and one for the inverted.
Your code does therefore the very same like that here:
signal srp, srn : std_logic_vector (1 downto 0);

process (nClockIn) begin
  if rising_edge(nClockIn) then
    -- sync in input signal
    srp <= srp(0) & InputSignal;
    srn <= srn(0) & (not InputSignal);
 
    -- check for edges
    FallOutput <= '1' when srp = "10" else '0';
    RiseOutput <= '1' when srn = "10" else '0';
  end if;
end process;
And it can be shortened to this:
signal sr : std_logic_vector (1 downto 0);

process (nClockIn) begin
  if rising_edge(nClockIn) then
    -- sync in input signal
    sr <= sr(0) & InputSignal;
 
    -- check for edges
    FallOutput <= '1' when sr = "10" else '0';
    RiseOutput <= '1' when sr = "01" else '0';
  end if;
end process;


> Excuse me
No problem. You do it your way, I do it mine. And be sure: I learn from 
your code...

: Edited by Moderator
von Alexander S. (Company: Home) (alex_isr)


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Lothar M. wrote:
> I learn from your code...

 Thanx.

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