Attached ModelSim VHDL design of signal Rise/Fall Detector. Regards Alex.
Attached files:
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DigDef.png
430 KB
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Edited by User
To keep things short I use shift a 3 bit shift register:
1 | -- sync in input signal
|
2 | sr <= sr(1 downto 0) & InputSignal when rising_edge(clk); |
3 | |
4 | -- check for edges
|
5 | FallOutput <= '1' when sr(2 downto 1) = "10" else '0'; |
6 | RiseOutput <= '1' when sr(2 downto 1) = "01" else '0'; |
I do not use a reset for such simple tasks, because I can't see no benefit.
What max. delay you have ? How many clocks ? Your outputs does not clocked !!!
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Edited by User
Alexander S. wrote: > What max. delay you have ? On the output one clock less than your design (your design has unnecessary latency). > How many clocks ? Ideally only one clock in the whole design. > Your outputs does not clocked !!! Yes, because - it's not necessary when the whole rest of the design is clocked - there's no additional latency due to unnecessary flipflops in my design BTW: your question are very entry level. You simply can answer them yourself. Just implement my three lines in your code.
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Edited by Moderator
Attached files:
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DigDef_Delay.png
56 KB
Lothar M. wrote: >> How many clocks ? > Ideally only one clock in the whole design. Excuse me, but my design have delay from 0.5 to 1.5 clocks with synchronous output. Regards Alex.
Alexander S. wrote: > with synchronous output. What I say is: there is no need for a synchronous output when the ongoing stages are synchronous. Syncing just adds latency, becasuse syncing adds flipflops. Alexander S. wrote: > but my design
1 | PipeLine: |
2 | process (ClockIn) |
3 | begin
|
4 | if(ClockIn'event and ClockIn = '1') then |
5 | case nResetIn is |
6 | when '0' => |
7 | InputSignalF <= '0'; |
8 | InputSignalFf <= '0'; |
9 | nInputSignalF <= '1'; |
10 | nInputSignalFf <= '1'; |
11 | when others => |
12 | InputSignalF <= InputSignal ; |
13 | InputSignalFf <= InputSignalf ; |
14 | nInputSignalF <= not InputSignal ; |
15 | nInputSignalFf <= nInputSignalF ; |
16 | end case; |
17 | end if; |
18 | end process PipeLine; |
19 | |
20 | OutProcess: |
21 | process(nClockIn) |
22 | begin
|
23 | if (nClockIn'event and nClockIn = '1') then |
24 | case nResetIn is |
25 | when '0' => |
26 | RiseOutput <= '0'; |
27 | FallOutput <= '0'; |
28 | when others => |
29 | RiseOutput <= InputSignalF and ( not InputSignalFf ); |
30 | FallOutput <= nInputSignalF and ( not nInputSignalFf ); |
31 | end case; |
32 | end if; |
33 | end process OutProcess; |
Your design has 2 shift register of each 2 bits length. One is for the direct input signal and one for the inverted. Your code does therefore the very same like that here:
1 | signal srp, srn : std_logic_vector (1 downto 0); |
2 | |
3 | process (nClockIn) begin |
4 | if rising_edge(nClockIn) then |
5 | -- sync in input signal
|
6 | srp <= srp(0) & InputSignal; |
7 | srn <= srn(0) & (not InputSignal); |
8 | |
9 | -- check for edges
|
10 | FallOutput <= '1' when srp = "10" else '0'; |
11 | RiseOutput <= '1' when srn = "10" else '0'; |
12 | end if; |
13 | end process; |
And it can be shortened to this:
1 | signal sr : std_logic_vector (1 downto 0); |
2 | |
3 | process (nClockIn) begin |
4 | if rising_edge(nClockIn) then |
5 | -- sync in input signal
|
6 | sr <= sr(0) & InputSignal; |
7 | |
8 | -- check for edges
|
9 | FallOutput <= '1' when sr = "10" else '0'; |
10 | RiseOutput <= '1' when sr = "01" else '0'; |
11 | end if; |
12 | end process; |
> Excuse me
No problem. You do it your way, I do it mine. And be sure: I learn from
your code...
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Edited by Moderator
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