EmbDev.net

Forum: FPGA, VHDL & Verilog VHDL optimization


von Kilian H. (jal)


Rate this post
useful
not useful
I've been wondering how much optimization the average tool performs, and 
how much I should manually try to optimize. For example, if I have two 
signals with the same assignment:
1
   sig1 <= (someSig & "000") + someOtherSig;
2
   sig2 <= (someSig & "000") + someOtherSig;
are the tools smart enough to know it's the same assignment and merge 
them? Or should I create a variable and use that?

A second example, would the below create the same logic, or is one 
preferable to the other? If so why?
1
   if sig1 = '0' then
2
     sig2 <= "0000";
3
   else
4
     sig2 <= "1111";
5
   end if;
6
7
   sig2 <= sig1 & sig1 & sig1 & sig1;

von -gb- (Guest)


Rate this post
useful
not useful
Write the code simple to read and understand. The tools normally 
optimize better than you could do.

von Christoph Z. (christophz)


Rate this post
useful
not useful
Kilian H. wrote:
> For example, if I have two
> signals with the same assignment:
> are the tools smart enough to know it's the same assignment and merge
> them?

Yes, they are smart enough to merge them even when they are declared in 
different files.

Kilian H. wrote:
> A second example, would the below create the same logic, or is one
> preferable to the other? If so why?

In the simulation it is definitely NOT equivalent (due to the fact that 
std_logic has more than '0' and '1').

I would assume that the if construct synthesizes to a multiplexer 
structure.

The second one could be written as sig2 <= (others => sig1);

von Kilian H. (jal)


Rate this post
useful
not useful
Thanks both, good to know the optimizers are smart enough, saves me some 
headaches :).

@ChristofZ: hadn't thought of using (others => sig1), thanks!

Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
No account? Register here.