VHDL optimizationI've been wondering how much optimization the average tool performs, and how much I should manually try to optimize. For example, if I have two signals with the same assignment:
are the tools smart enough to know it's the same assignment and merge them? Or should I create a variable and use that? A second example, would the below create the same logic, or is one preferable to the other? If so why?
Guest
#6279481
Write the code simple to read and understand. The tools normally optimize better than you could do. Kilian H. wrote: > For example, if I have two > signals with the same assignment: > are the tools smart enough to know it's the same assignment and merge > them? Yes, they are smart enough to merge them even when they are declared in different files. Kilian H. wrote: > A second example, would the below create the same logic, or is one > preferable to the other? If so why? In the simulation it is definitely NOT equivalent (due to the fact that std_logic has more than '0' and '1'). I would assume that the if construct synthesizes to a multiplexer structure. The second one could be written as sig2 <= (others => sig1); Thanks both, good to know the optimizers are smart enough, saves me some headaches :). @ChristofZ: hadn't thought of using (others => sig1), thanks! Reply |