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Forum: FPGA, VHDL & Verilog Stopwatch in VHDL


von Andrew (Guest)


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Hello everyone!
Is it possible to create stopwatch in VHDL with 4 times memory? Start 
and stop on the one button, memory set on the second button. One second 
accuracy

von -gb- (Guest)


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Offcourse, Sure, freilich, if you can draw a state diagram at least in 
your mind. With the right hardware this precision is also possible.

But a cheap microcontroller would also fit the task.

von Andrew (Guest)


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How to start with code?

von -gb- (Guest)


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If you don't have a Städte concept in your mind then draw one first.

What are the inputs and outputs?

And then write the neccessary logic.

von -gb- (Guest)


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von Andrew (Guest)


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I wrote this...

What do you think?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Stoper is
port(  CLK, onOFF, memPUSH, reset : in STD_LOGIC;
    sec, min, hour, mem1s, mem1m, mem1h  : out STD_LOGIC_VECTOR(5 downto 0) := "000000";
    mem2s, mem2m, mem2h, mem3s, mem3m, mem3h : out STD_LOGIC_VECTOR(5 downto 0) := "000000");  
end Stoper;

architecture Behavioral of Stoper is
signal S : STD_LOGIC_VECTOR(5 downto 0) := "111000";
signal M, H, P1S, P1M, P1H : STD_LOGIC_VECTOR(5 downto 0) := "000000";
signal P2S, P2M, P2H, P3S, P3M, P3H : STD_LOGIC_VECTOR(5 downto 0) := "000000";
signal stan : STD_LOGIC := '0';
signal memS : STD_LOGIC_VECTOR(1 downto 0) := "00";
begin
  process(onOFF)
  begin
    if (onOFF'event and onOFF = '1') then
      stan <= not stan;
    end if;
  end process;
  
  process(memPUSH, reset)
  begin
    if (memPUSH'event and memPUSH = '1' and memS = "00") then
        P1S <= S;
        P1M <= M;
        P1H <= H;
        memS <= "01";
    end if;
    
    if (memPUSH'event and memPUSH = '1' and memS = "01") then
        P2S <= S;
        P2M <= M;
        P2H <= H;
        memS <= "11";
    end if;
    
    if (memPUSH'event and memPUSH = '1' and memS = "11") then
        P3S <= S;
        P3M <= M;
        P3H <= H;
        memS <= "00";
    end if;
    
    if (reset > '0') then
        P1S <= "000000";
        P1M <= "000000";
        P1H <= "000000";
        P2S <= "000000";
        P2M <= "000000";
        P2H <= "000000";
        P3S <= "000000";
        P3M <= "000000";
        P3H <= "000000";
        memS <= "11";
    end if;
  end process;
  
  process(CLK, stan, reset)
  begin
    if(stan = '1') then
      if (clk'event and clk = '1') then
        S <= S + 1;
      end if;
    
      if (S = "111011") then
        M <= M + 1;
        S <= "000000";
        
        if (M = "111011") then
        H <= H + 1;
        M <= "000000";  
        end if;
      end if;
    
    end if;
    
    if (reset > '0') then
      S <= "000000";
      M <= "000000";
      H <= "000000";
    end if;
  end process;
  
  sec <= S;
  min <= M;
  hour <= H;
  mem1s <= P1S;
  mem1m <= P1M;
  mem1h <= P1H;
  mem2s <= P2S;
  mem2m <= P2M;
  mem2h <= P2H;
  mem3s <= P3S;
  mem3m <= P3M;
  mem3h <= P3H;

end Behavioral;

: Edited by Moderator
von Duke Scarring (Guest)


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Andrew wrote:
> What do you think?
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;

Doing calculations with std_logic_unsigned or std_logic_signed is very 
bad style. Just use only the numeric_std library (which is really a IEEE 
standard) for calculations and do correct casting/convertion:
https://www.doulos.com/knowhow/vhdl_designers_guide/numeric_std/

Duke

von Christoph Z. (christophz)


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Andrew wrote:
> process(onOFF)
>   begin
>     if (onOFF'event and onOFF = '1') then
>       stan <= not stan;
>     end if;
>   end process;

Is this code only for simulation? You will have troubles synthesizing 
this part.

Andrew wrote:
> if(stan = '1') then
>       if (clk'event and clk = '1') then
>         S <= S + 1;
>       end if;

Are you really sure that you want to have a gated clock? What device are 
you targeting, does it support gated clocks? Some FPGAs support it but 
not all.

von Lothar M. (lkmiller) (Moderator)


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Christoph Z. wrote:
> Are you really sure that you want to have a gated clock?
Luckily it's not leading to a gated clock, but it is a very strange and 
obfuscating way to write a clock enable.

See sel3 there:
http://www.lothar-miller.de/s9y/categories/6-Clock-Enable


Andrew wrote:
> What do you think?
Way to much clocks in that design. Each 'event acts like a clock source 
for flipflops. Thats no good design practice.
The proper way to generate clocks inside an FPGA is by using the clock 
managers.
And a usual beginners design has only and exactly one clock all over.

Very, very strange coding style in those lines of the "process(memPUSH, 
reset)". Where did you find this?
To react to a button the usual way is:
1. sync it in
2. debounce it
3. set an edge detection on it
4. use it

>  if (S = "111011") then
Why don't you use integers for the counters? Then this line would look 
much better readable for humans:
if S=59 then

Finally it will be very tricky to display your binary H:M:S values on 
e.g. 7 segment displays. Because therfore you will have to spit it up 
into h10, h1, m10, m1, s10 and s1. So the most easy way would be to 
count each segment for itself like id did it there:
http://www.lothar-miller.de/s9y/archives/88-VHDL-vs.-Verilog-am-Beispiel-einer-Stoppuhr.html

BTW: Pls use the [vhdl] tags to wrap your code

: Edited by Moderator

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