Hello everyone! Is it possible to create stopwatch in VHDL with 4 times memory? Start and stop on the one button, memory set on the second button. One second accuracy
Offcourse, Sure, freilich, if you can draw a state diagram at least in your mind. With the right hardware this precision is also possible. But a cheap microcontroller would also fit the task.
If you don't have a Städte concept in your mind then draw one first. What are the inputs and outputs? And then write the neccessary logic.
Sorry meant state concept like here: https://bennthomsen.files.wordpress.com/2011/12/stop-watch-state-diagram.png?w=584 https://www.researchgate.net/profile/Timothy_Fossum/publication/234780032/figure/fig5/AS:323378541023234@1454110860075/The-state-diagram-for-the-three-button-stopwatch.png https://www.researchgate.net/profile/Dr_Praveen_Srivastava/publication/215584753/figure/fig2/AS:305716725338120@1449899955646/Stopwatch-behavior-all-state-coverage.png It is called finite state machine (fsm). if you have decided how your fsm should look and which states it should have, you can write it in hdl.
I wrote this... What do you think?
1 | library IEEE; |
2 | use IEEE.STD_LOGIC_1164.ALL; |
3 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
4 | |
5 | entity Stoper is |
6 | port( CLK, onOFF, memPUSH, reset : in STD_LOGIC; |
7 | sec, min, hour, mem1s, mem1m, mem1h : out STD_LOGIC_VECTOR(5 downto 0) := "000000"; |
8 | mem2s, mem2m, mem2h, mem3s, mem3m, mem3h : out STD_LOGIC_VECTOR(5 downto 0) := "000000"); |
9 | end Stoper; |
10 | |
11 | architecture Behavioral of Stoper is |
12 | signal S : STD_LOGIC_VECTOR(5 downto 0) := "111000"; |
13 | signal M, H, P1S, P1M, P1H : STD_LOGIC_VECTOR(5 downto 0) := "000000"; |
14 | signal P2S, P2M, P2H, P3S, P3M, P3H : STD_LOGIC_VECTOR(5 downto 0) := "000000"; |
15 | signal stan : STD_LOGIC := '0'; |
16 | signal memS : STD_LOGIC_VECTOR(1 downto 0) := "00"; |
17 | begin
|
18 | process(onOFF) |
19 | begin
|
20 | if (onOFF'event and onOFF = '1') then |
21 | stan <= not stan; |
22 | end if; |
23 | end process; |
24 | |
25 | process(memPUSH, reset) |
26 | begin
|
27 | if (memPUSH'event and memPUSH = '1' and memS = "00") then |
28 | P1S <= S; |
29 | P1M <= M; |
30 | P1H <= H; |
31 | memS <= "01"; |
32 | end if; |
33 | |
34 | if (memPUSH'event and memPUSH = '1' and memS = "01") then |
35 | P2S <= S; |
36 | P2M <= M; |
37 | P2H <= H; |
38 | memS <= "11"; |
39 | end if; |
40 | |
41 | if (memPUSH'event and memPUSH = '1' and memS = "11") then |
42 | P3S <= S; |
43 | P3M <= M; |
44 | P3H <= H; |
45 | memS <= "00"; |
46 | end if; |
47 | |
48 | if (reset > '0') then |
49 | P1S <= "000000"; |
50 | P1M <= "000000"; |
51 | P1H <= "000000"; |
52 | P2S <= "000000"; |
53 | P2M <= "000000"; |
54 | P2H <= "000000"; |
55 | P3S <= "000000"; |
56 | P3M <= "000000"; |
57 | P3H <= "000000"; |
58 | memS <= "11"; |
59 | end if; |
60 | end process; |
61 | |
62 | process(CLK, stan, reset) |
63 | begin
|
64 | if(stan = '1') then |
65 | if (clk'event and clk = '1') then |
66 | S <= S + 1; |
67 | end if; |
68 | |
69 | if (S = "111011") then |
70 | M <= M + 1; |
71 | S <= "000000"; |
72 | |
73 | if (M = "111011") then |
74 | H <= H + 1; |
75 | M <= "000000"; |
76 | end if; |
77 | end if; |
78 | |
79 | end if; |
80 | |
81 | if (reset > '0') then |
82 | S <= "000000"; |
83 | M <= "000000"; |
84 | H <= "000000"; |
85 | end if; |
86 | end process; |
87 | |
88 | sec <= S; |
89 | min <= M; |
90 | hour <= H; |
91 | mem1s <= P1S; |
92 | mem1m <= P1M; |
93 | mem1h <= P1H; |
94 | mem2s <= P2S; |
95 | mem2m <= P2M; |
96 | mem2h <= P2H; |
97 | mem3s <= P3S; |
98 | mem3m <= P3M; |
99 | mem3h <= P3H; |
100 | |
101 | end Behavioral; |
:
Edited by Moderator
Andrew wrote: > What do you think? > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; Doing calculations with std_logic_unsigned or std_logic_signed is very bad style. Just use only the numeric_std library (which is really a IEEE standard) for calculations and do correct casting/convertion: https://www.doulos.com/knowhow/vhdl_designers_guide/numeric_std/ Duke
Andrew wrote: > process(onOFF) > begin > if (onOFF'event and onOFF = '1') then > stan <= not stan; > end if; > end process; Is this code only for simulation? You will have troubles synthesizing this part. Andrew wrote: > if(stan = '1') then > if (clk'event and clk = '1') then > S <= S + 1; > end if; Are you really sure that you want to have a gated clock? What device are you targeting, does it support gated clocks? Some FPGAs support it but not all.
Christoph Z. wrote: > Are you really sure that you want to have a gated clock? Luckily it's not leading to a gated clock, but it is a very strange and obfuscating way to write a clock enable. See sel3 there: http://www.lothar-miller.de/s9y/categories/6-Clock-Enable Andrew wrote: > What do you think? Way to much clocks in that design. Each 'event acts like a clock source for flipflops. Thats no good design practice. The proper way to generate clocks inside an FPGA is by using the clock managers. And a usual beginners design has only and exactly one clock all over. Very, very strange coding style in those lines of the "process(memPUSH, reset)". Where did you find this? To react to a button the usual way is: 1. sync it in 2. debounce it 3. set an edge detection on it 4. use it > if (S = "111011") then Why don't you use integers for the counters? Then this line would look much better readable for humans: if S=59 then Finally it will be very tricky to display your binary H:M:S values on e.g. 7 segment displays. Because therfore you will have to spit it up into h10, h1, m10, m1, s10 and s1. So the most easy way would be to count each segment for itself like id did it there: http://www.lothar-miller.de/s9y/archives/88-VHDL-vs.-Verilog-am-Beispiel-einer-Stoppuhr.html BTW: Pls use the [vhdl] tags to wrap your code
:
Edited by Moderator
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