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Forum: FPGA, VHDL & Verilog Timer with alarm in VHDL


von Carl (Guest)


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Hi! Is it possible to create Timer with alarm function in VHDL? How to 
start create it?

von Lothar M. (lkmiller) (Moderator)


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Carl wrote:
> Is it possible to create Timer with alarm function in VHDL?
Yes.

> How to start create it?
Somehow like this:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity stopwatch is
    Port ( clock    : in  STD_LOGIC;
           reset    : in  STD_LOGIC;
           -- add your ports for dsplay, buttons and speaker/beeper
    :
    :

> How to start create it?
- Generate a one-second pulse.
- Count the seconds, and the minutes and the hours.
- Display those counter vaules on some kind of display.
- Compare the counters with an alarm time and generate a sound on a 
speaker.

> How to start create it?
Maybe you can get a basic idea from there:
http://www.lothar-miller.de/s9y/archives/88-VHDL-vs.-Verilog-am-Beispiel-einer-Stoppuhr.html
Ty google translator, its German. But the VHDL code is nealy 
self-explaining... ;-)

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