I am trying to design MASH 111 DDSM using verilog. I have attatched the code. But output is "xxx" always. Can someone help?
GAURAV G. wrote: > But output is "xxx" always. What do you expect instead? And why? > Can someone help? Do you have a testbench? If so: post it. If not: create one. https://verilogguide.readthedocs.io/en/latest/verilog/testbench.html