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Forum: FPGA, VHDL & Verilog Implementation of MASH 111 in verilog


von GAURAV G. (Company: student) (gaurav8171)


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I am trying to design MASH 111 DDSM using verilog.
I have attatched the code.
But output is "xxx" always.
Can someone help?

von Lothar M. (lkmiller) (Moderator)


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GAURAV G. wrote:
> But output is "xxx" always.
What do you expect instead? And why?

> Can someone help?
Do you have a testbench?
If so: post it.
If not: create one.
https://verilogguide.readthedocs.io/en/latest/verilog/testbench.html

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