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Forum: FPGA, VHDL & Verilog D Flip-Flop VHDL code


von Josh (Guest)


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Hi!

Can anybody help me with D-Flip Flop with synchronous set and reset and 
clock enable? I was trying write this code, but actually i can't

von -gb- (Guest)


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Greetings!

Untested:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity dff is port(
  nCLR : in std_logic;
  nPR : in std_logic;
  D : in std_logic;
  CP : in std_logic;
  Q : out std_logic;
  nQ : out std_logic);
end entity dff;
 
architecture behav of dff is

begin

process (nCLR, nPR, CP) begin
  if nCLR = '0' then
    Q <= '0';
    nQ <= '1';
  elsif nPR = '0' then
    Q <= '1';
    nQ <= '0';
  elsif rising_edge(CP) then
    Q <= D;
    nQ <= not D;
  end if;
end process;



end architecture behav;

von ktorkkelson (Guest)


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Hi, all.

Not completely correct, unfortunately. The description above has an 
asynchnonous(!) set and reset, and is also missing a clock enable.
...
process (clk) begin
  if rising_edge(clk) then
    if (set = '1') then
      Q  <= '1';
    elsif (clear = '1') then
      Q  <= '0';
    elsif (clk_en = '1') then
      Q  <= D;
    end if;  
  end if;
end process;
...

Cheers

von -gb- (Guest)


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Sorry ...

von Lothar M. (lkmiller) (Moderator)


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Josh wrote:
> Can anybody help me with D-Flip Flop with synchronous set and reset and
> clock enable?
That is nearby the most simple exercise after "assign an output to an 
input". You should get the trick on that before going on...

> I was trying write this code, but actually i can't
Show what you have and tell us what problems you encounter. Then we 
can help you.

Otherwise we can continue posting several solutions and you will not be 
able to check out which one ist ok.

ktorkkelson wrote:
> The description above has an asynchnonous(!) set and reset
Getting a synchronous description for sure can be achived this way:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity dff is port(
  R   : in std_logic;
  S   : in std_logic;
  CE  : in std_logic;
  CLK : in std_logic;
  D   : in std_logic;
  Q   : out std_logic);
end entity dff;
 
architecture behav of dff is

begin

  process begin
    wait until rising_edge(CLK);
    if    R = '1' then -- reset has priority over set
      Q <= '0';
    elsif S = '1' then
      Q <= '1';
    elsif CE = '1' then
      Q <= D;
    end if;
  end process;

end architecture behav;

: Edited by Moderator
von Josh (Guest)


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Ok, so it is D Flip-Flop with Synchronous Reset, Synchronous Set and 
Clock Enable?

von Lothar M. (lkmiller) (Moderator)


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Josh wrote:
> Ok, so it is D Flip-Flop with Synchronous Reset, Synchronous Set and
> Clock Enable?
Check it out with the simulator. Its just 7 lines you have to 
understand.

von Josh (Guest)


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Isn't it asynchronous reset in this code?

von Christophz (Guest)


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Josh wrote:
> Isn't it asynchronous reset in this code?

Which one? Pick one, you have a 50:50 chance :-)

von Lothar M. (lkmiller) (Moderator)


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Josh wrote:
> Isn't it asynchronous reset in this code?
You forgot to attach "this code" of yours.

Christophz wrote:
> Which one? Pick one, you have a 50:50 chance :-)
Based on the 3 code samples I calculate a fairly good 66% chance to get 
a completely synchronous flipflop.

von Alexander S. (Company: Home) (alex_isr)


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Josh wrote:
> Hi!
>
> Can anybody help me with D-Flip Flop with synchronous set and reset and
> clock enable? I was trying write this code, but actually i can't


I think it's may be :
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity dff is port(
  nCLR     : in std_logic;
  nPR      : in std_logic;
  D        : in std_logic;
  ClockIn  : in std_logic;
  ClockEn  : in std_logic;
  Q_Out    : out std_logic;
  nQ_Out   : out std_logic);
end entity dff;

architecture behav of dff is
signal Q,nQ : std_logic;

begin

  Q_Out   <= Q;
  nQ_Out   <= nQ;


 DFF_Process:
process (ClockIn)
 variable SetReset : std_logic_vector(1 downto 0);
begin
SetReset(0) := nCLR;
SetReset(1) := nPR;
 if(ClockIn'event and ClockIn = '1') then
  case SetReset is
   when "00" =>                                                                 -- No operation
     Q <= Q;
    nQ <= nQ;
   when "01"  =>                                                                -- nPR active
     Q <= '1';
    nQ <= '0';
   when "10"  =>                                                                -- nCLR active
    Q  <= '0';
    nQ <= '1';
   when others =>
    if(ClockEn = '1') then
     Q  <= D;
     nQ <= not D;
    else
     Q  <= Q;
     nQ <= nQ;
    end if;
  end case;
 end if;
end process  DFF_Process;

end architecture behav;

: Edited by User
von Lothar M. (lkmiller) (Moderator)


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Alexander S. wrote:
> nCLR     : in std_logic;
> nPR      : in std_logic;
That means for me that CLEAR and PRESET are active, when they are '0'. 
So the "forbidden" input combination is "00". But in your incredible 
spaciuos written code that is the only combination where the input are 
stored.

But in your code "00" is the "normal" state, in which the data input is 
stored in the flipflop with each clock.

And also usually CLEAR and PRESET are inputs for an asynchronous 
flipflop. Synchronous flipflops have SET and RESET inputs (but beware: 
RS-Flipflops also have SET and RESET, but no clock)

>   when "00" =>                -- No operation
Usually a synchronous flipflop with SET and RESET has a priotity on 
those two inputs: the RESET input his the most important. When RESET is 
active, then its not relevant what level the SET and D inputs have.

von Alexander S. (Company: Home) (alex_isr)


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Lothar M. wrote:

> And also usually CLEAR and PRESET are inputs for an asynchronous flipflop.

 But

Josh wrote:
> Hi!
>
> Can anybody help me with D-Flip Flop with synchronous set and reset and
> clock enable?

 Regards Alex.

: Edited by User
von Alexander S. (Company: Home) (alex_isr)


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Lothar M. wrote:
> Alexander S. wrote:
>> nCLR     : in std_logic;
>> nPR      : in std_logic;
> That means for me that CLEAR and PRESET are active, when they are '0'.
> So the "forbidden" input combination is "00". But in your incredible
> spaciuos written code that is the only combination where the input are
> stored.
>
> But in your code "00" is the "normal" state, in which the data input is
> stored in the flipflop with each clock.

  State "00" is wrong state .
 Designer must lock and prevent this state.

 In design we can't leave this state not defined.

 FlipFlop always have state '0' or '1'.

 In my design : if designer not prevented wrong input state "00" , Flip 
Flop
 save it last state and do not save/received input state.

 Regards Alex.

: Edited by User

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