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Forum: FPGA, VHDL & Verilog D Flip-Flop VHDL code


von Josh (Guest)


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Hi!

Can anybody help me with D-Flip Flop with synchronous set and reset and 
clock enable? I was trying write this code, but actually i can't

von -gb- (Guest)


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Greetings!

Untested:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity dff is port(
  nCLR : in std_logic;
  nPR : in std_logic;
  D : in std_logic;
  CP : in std_logic;
  Q : out std_logic;
  nQ : out std_logic);
end entity dff;
 
architecture behav of dff is

begin

process (nCLR, nPR, CP) begin
  if nCLR = '0' then
    Q <= '0';
    nQ <= '1';
  elsif nPR = '0' then
    Q <= '1';
    nQ <= '0';
  elsif rising_edge(CP) then
    Q <= D;
    nQ <= not D;
  end if;
end process;



end architecture behav;

von ktorkkelson (Guest)


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Hi, all.

Not completely correct, unfortunately. The description above has an 
asynchnonous(!) set and reset, and is also missing a clock enable.
...
process (clk) begin
  if rising_edge(clk) then
    if (set = '1') then
      Q  <= '1';
    elsif (clear = '1') then
      Q  <= '0';
    elsif (clk_en = '1') then
      Q  <= D;
    end if;  
  end if;
end process;
...

Cheers

von -gb- (Guest)


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Sorry ...

von Lothar M. (lkmiller) (Moderator)


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Josh wrote:
> Can anybody help me with D-Flip Flop with synchronous set and reset and
> clock enable?
That is nearby the most simple exercise after "assign an output to an 
input". You should get the trick on that before going on...

> I was trying write this code, but actually i can't
Show what you have and tell us what problems you encounter. Then we 
can help you.

Otherwise we can continue posting several solutions and you will not be 
able to check out which one ist ok.

ktorkkelson wrote:
> The description above has an asynchnonous(!) set and reset
Getting a synchronous description for sure can be achived this way:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity dff is port(
  R   : in std_logic;
  S   : in std_logic;
  CE  : in std_logic;
  CLK : in std_logic;
  D   : in std_logic;
  Q   : out std_logic);
end entity dff;
 
architecture behav of dff is

begin

  process begin
    wait until rising_edge(CLK);
    if    R = '1' then -- reset has priority over set
      Q <= '0';
    elsif S = '1' then
      Q <= '1';
    elsif CE = '1' then
      Q <= D;
    end if;
  end process;

end architecture behav;

: Edited by Moderator
von Josh (Guest)


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Ok, so it is D Flip-Flop with Synchronous Reset, Synchronous Set and 
Clock Enable?

von Lothar M. (lkmiller) (Moderator)


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Josh wrote:
> Ok, so it is D Flip-Flop with Synchronous Reset, Synchronous Set and
> Clock Enable?
Check it out with the simulator. Its just 7 lines you have to 
understand.

von Josh (Guest)


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Isn't it asynchronous reset in this code?

von Christophz (Guest)


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Josh wrote:
> Isn't it asynchronous reset in this code?

Which one? Pick one, you have a 50:50 chance :-)

von Lothar M. (lkmiller) (Moderator)


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Josh wrote:
> Isn't it asynchronous reset in this code?
You forgot to attach "this code" of yours.

Christophz wrote:
> Which one? Pick one, you have a 50:50 chance :-)
Based on the 3 code samples I calculate a fairly good 66% chance to get 
a completely synchronous flipflop.

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