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Forum: FPGA, VHDL & Verilog I am not able to convert MATLAB code to VHDL


von Abel B. (abel_b)


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i am trying to convert Matlab code.Thanks it I can finde peaks in a 
signal. On the other hand, in VHDL We have an input each clk_period, but 
a can discard one in two if it was necessary. I am not able to see or 
use this code in VHDL. If I use a FSM I think that it takes longer to 
cycle through all states than it does for a new sample to arrive and 
restart the process. Can anyone help me? Thanks a lot!!

von Lothar M. (lkmiller) (Moderator)


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Abel B. wrote:
> I am not able to see or use this code
What does that code do?
If you don't know that you must analyze it.

> If I use a FSM I think that it takes longer to cycle through all states
> than it does for a new sample to arrive and restart the process.
As far as I see you will not need a FSM in hardware. Because there you 
don't get the data readily in an array, but instead one after each other 
as a continuous stream.

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