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Forum: FPGA, VHDL & Verilog DTW in Verilog


DTW in Verilog
von Sebastian Taylor (Guest)

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So im working on a project and we have a problem making a dynamic time 
wrapping in verilog. Is there anyone who know how to write DTW in 
verilog ? Please help...

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Re: DTW in Verilog
von Duke Scarring (Guest)

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Sebastian Taylor wrote:
> dynamic time wrapping
Can you explain this term? I never heard it before.
And where is the relation to a hardware description language like 
verilog?

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Re: DTW in Verilog
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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Sebastian Taylor wrote:
> dynamic time wrapping
Do you mean this: https://en.wikipedia.org/wiki/Dynamic_time_warping

> Is there anyone who know how to write DTW in verilog ?
Just for simulation?
Or for implemenatation on real hardware?
If the second: whats your target hardware?
How much experience do you have with that hareware and with Verilog?
Do you use an embedded processor (hard- or softcore) on that hardware?

As time warping is a algorithmic problem you can get the algorithm 
somewhere in a book or online and you just have to implement on your 
platform. When you have to deal with real hardware, then you will check 
out how you can access memory to store and fetch data. Then you will 
have to implement a processor for the algorithm.

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