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Forum: FPGA, VHDL & Verilog Counter up/down


Counter up/down
von John (Guest)

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I will use seven segment display to show the numbers, but I also must be 
able to set a specific time by increasing/decreasing and then once it is 
set, with another button the clock will start to go down.

signal lock is for preventing the count increases at the speed of the

manual is a button,

I guess the count up is okay, but the problem is when I want it to go 
down. In the simulation when I put the sentido HIGH then I do not get 
anything and does not work.

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library ieee;

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use ieee.std_logic_1164.all;

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use IEEE.STD_LOGIC_UNSIGNED.ALL;

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entity counter is

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port(   clck, reset : in std_logic;

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        limit   : in integer range 0 to 10;

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        manual: inout std_logic;

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        sentido: in std_logic;

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        bitcount : out std_logic_vector(3 downto 0);

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        clckout : out std_logic);

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end counter;

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architecture behavior of counter is

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signal Cs : std_logic_vector(3 downto 0):="0000";

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signal lock: std_logic;

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begin   

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Count : process(clck,reset,manual,lock,sentido)

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    begin

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            if(rising_edge(clck))then

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             if (manual='0' and lock ='0') then

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                      Cs<=Cs+1;

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                       lock<='1';

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             elsif(manual='1' and lock='1' ) then        

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                     lock<='1';

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             else

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                     lock<='0';

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                    end if; 

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                    end if;

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    if sentido = '1' then

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                 Cs<=Cs-1;

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                    end if;

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            if (reset = '1') then

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                    Cs <="0000";

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                end if;

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                if (Cs = "1010") then

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                      Cs <= "0000";

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                end if;

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end process Count;

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bitcount <=Cs;

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end behavior;


  


  



  

  
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    Re: Counter up/down
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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John wrote:
> In the simulation when I put the sentido HIGH then I do not get anything
Absolutely NOTHING?
> and does not work.
What does your simulation show instead of the desired reaction?


What you built there is a combinatorial loop, because the Cs<=Cs-1 
path has no clock!!11one!eleven!11
Where did you find this very strange way of a synchronous process? How 
do it all the others around the world?

Try this and think about it:
1
-- only the clock and (if absolutely necessary) the reset in the sensitivity list of a synchronous process!

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Count : process(clck,reset) 

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    begin

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      -- the reset path (is it really necessary?)

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      if (reset = '1') then

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              Cs <="0000";

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      -- the one and only clock for the synchronous path

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      elsif rising_edge(clck) then

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             if (manual='0' and lock ='0') then

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                      Cs<=Cs+1;

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                       lock<='1';

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             elsif(manual='1' and lock='1' ) then        

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                     lock<='1';

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             else

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                     lock<='0';

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             end if; 

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             if sentido = '1' then      

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                  Cs<=Cs-1;

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             end if;

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             if Cs = "1010" then

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                      Cs <= "0000";

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             end if;

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      end if;

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end process Count;


BTW: pls use the [vhdl] tags to wrap your VHDL code.

  


  



  

  
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