# Forum: FPGA, VHDL & Verilog Counter up/down

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I will use seven segment display to show the numbers, but I also must be
able to set a specific time by increasing/decreasing and then once it is
set, with another button the clock will start to go down.

signal lock is for preventing the count increases at the speed of the

manual is a button,

I guess the count up is okay, but the problem is when I want it to go
down. In the simulation when I put the sentido HIGH then I do not get
anything and does not work.

 library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter is port( clck, reset : in std_logic; limit : in integer range 0 to 10; manual: inout std_logic; sentido: in std_logic; bitcount : out std_logic_vector(3 downto 0); clckout : out std_logic); end counter; architecture behavior of counter is signal Cs : std_logic_vector(3 downto 0):="0000"; signal lock: std_logic; begin Count : process(clck,reset,manual,lock,sentido) begin if(rising_edge(clck))then if (manual='0' and lock ='0') then Cs<=Cs+1; lock<='1'; elsif(manual='1' and lock='1' ) then lock<='1'; else lock<='0'; end if; end if; if sentido = '1' then Cs<=Cs-1; end if; if (reset = '1') then Cs <="0000"; end if; if (Cs = "1010") then Cs <= "0000"; end if; end process Count; bitcount <=Cs; end behavior; 

: Edited by Moderator

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John wrote:
> In the simulation when I put the sentido HIGH then I do not get anything
Absolutely NOTHING?
> and does not work.

What you built there is a combinatorial loop, because the Cs<=Cs-1
path has no clock!!11one!eleven!11
Where did you find this very strange way of a synchronous process? How
do it all the others around the world?

Try this and think about it:
 -- only the clock and (if absolutely necessary) the reset in the sensitivity list of a synchronous process! Count : process(clck,reset) begin -- the reset path (is it really necessary?) if (reset = '1') then Cs <="0000"; -- the one and only clock for the synchronous path elsif rising_edge(clck) then if (manual='0' and lock ='0') then Cs<=Cs+1; lock<='1'; elsif(manual='1' and lock='1' ) then lock<='1'; else lock<='0'; end if; if sentido = '1' then Cs<=Cs-1; end if; if Cs = "1010" then Cs <= "0000"; end if; end if; end process Count; 

BTW: pls use the [vhdl] tags to wrap your VHDL code.

: Edited by Moderator

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