EmbDev.net

Forum: FPGA, VHDL & Verilog Counter up/down


von John (Guest)


Rate this post
0 useful
not useful
I will use seven segment display to show the numbers, but I also must be 
able to set a specific time by increasing/decreasing and then once it is 
set, with another button the clock will start to go down.

signal lock is for preventing the count increases at the speed of the

manual is a button,

I guess the count up is okay, but the problem is when I want it to go 
down. In the simulation when I put the sentido HIGH then I do not get 
anything and does not work.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port(   clck, reset : in std_logic;
        limit   : in integer range 0 to 10;
        manual: inout std_logic;
        sentido: in std_logic;
        bitcount : out std_logic_vector(3 downto 0);
        clckout : out std_logic);
end counter;

architecture behavior of counter is
signal Cs : std_logic_vector(3 downto 0):="0000";
signal lock: std_logic;
begin   
Count : process(clck,reset,manual,lock,sentido)
    begin

            if(rising_edge(clck))then
             if (manual='0' and lock ='0') then
                      Cs<=Cs+1;
                       lock<='1';
             elsif(manual='1' and lock='1' ) then        
                     lock<='1';
             else
                     lock<='0';

                    end if; 
                    end if;

    if sentido = '1' then
                 Cs<=Cs-1;
                    end if;

            if (reset = '1') then
                    Cs <="0000";
                end if;
                if (Cs = "1010") then
                      Cs <= "0000";
                end if;
end process Count;
bitcount <=Cs;

end behavior;

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


Rate this post
0 useful
not useful
John wrote:
> In the simulation when I put the sentido HIGH then I do not get anything
Absolutely NOTHING?
> and does not work.
What does your simulation show instead of the desired reaction?


What you built there is a combinatorial loop, because the Cs<=Cs-1 
path has no clock!!11one!eleven!11
Where did you find this very strange way of a synchronous process? How 
do it all the others around the world?

Try this and think about it:
-- only the clock and (if absolutely necessary) the reset in the sensitivity list of a synchronous process!
Count : process(clck,reset) 
    begin
      -- the reset path (is it really necessary?)
      if (reset = '1') then
              Cs <="0000";
      -- the one and only clock for the synchronous path
      elsif rising_edge(clck) then
             if (manual='0' and lock ='0') then
                      Cs<=Cs+1;
                       lock<='1';
             elsif(manual='1' and lock='1' ) then        
                     lock<='1';
             else
                     lock<='0';
             end if; 

             if sentido = '1' then      
                  Cs<=Cs-1;
             end if;

             if Cs = "1010" then
                      Cs <= "0000";
             end if;
      end if;
end process Count;

BTW: pls use the [vhdl] tags to wrap your VHDL code.

: Edited by Moderator

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.