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Forum: FPGA, VHDL & Verilog Pwm code for FPGA in VHDL


von Mubasheer A. (Company: Student) (muba)


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Hi.
I am new here and new to FPGA.
I have a former board which consists virtex ll Pro FPGA I am practicing 
VHDL code in this and I am using ise design suite 10.1 version.
I wanna generate pwm output from 100 mMHz clock which is connected to my 
FPGA.
I just need a quick start idea for this.
In microcontrollers we use timers and comparator to generate pwm. What 
hardware I have to generate to achieve pwm output in VHDL?
I was thinking if I can possible to use wait statement for example: 
out1<= '1' ;
                       Wait for 10 ns;
                        Out1<='0' ;
                        Wait for 90ns;
When I synthesis I was getting and error for using wait statement.
Is there anyone who know I am I doing right or is there any other way to 
achive pwm output?
Thank you at the earliest.

von -gb- (Guest)


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Hello,
in the FPGA there is no Watch, so you cannot wait a Time value.

But you have a clock source. the 100 MHz. One clock cycle is 10 ns. So 
if you want to wait 10 ns, wait 1 clock cycle. if you want to wait 90 
ns, then wait 9 clock cycles.

This can be done with a counter, counting clock cycles. Depending on the 
countervalue, you set the pwm.

von Lothar M. (lkmiller) (Moderator)


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Mubasheer A. wrote:
> Is there anyone who know I am I doing right
For simulation your code is fine.
But for real life you will need a timer and a comparator(*).

> is there any other way to achive pwm output?
Its not that difficult: take any manual of any microcontroller, look up 
chapter "timers" section "PWM" an see how its done in real life.



(*) see this here:
http://www.lothar-miller.de/s9y/archives/54-PWM.html
Its German, but the VHDL code is straight forward and only a few lines. 
Easy to figure out, what is done how.

: Edited by Moderator
von Mubasheer A. (Company: Student) (muba)


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Hi.
Thank you for both of you for the useful information you have given 
for.. another question running in my mind and it's required for my 
design.
What if I have to generate pwm out 17us on time and 3us off time which 
is total period of 20 us and inverted output of this in another pin say 
for example PWMoutP and  PWMoutN. Like pair.what modification I have to 
do in the given code?
Thank you.

von Lothar M. (lkmiller) (Moderator)


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Mubasheer A. wrote:
> What if I have to generate pwm out 17us on time and 3us off time which
> is total period of 20 us and inverted output of this in another pin say
> for example PWMoutP and  PWMoutN.
Define "inverted output" with a timing diagram.

Given that PWMoutP is the desired PWM signal, then for a simple 
inversion you could simply write something like that:
PWMoutN <= not PWMoutP;

But maybe depending on your hardware you will need some dead time 
between the activation of the corresponding driver. Thats discussed in 
the text there:
http://www.lothar-miller.de/s9y/archives/58-Totzeit-fuer-H-Bruecke.html
German again, try Google translator...   ;-)

: Edited by Moderator
von -gb- (Guest)


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Mubasheer A. wrote:
> what modification I have to
> do in the given code?

Do you want to synthesize the code? Then write a code with a counter.

17 us are 1700 cycles of the 100 MHz clock and 3 us are 300 cycles oft 
the 100 MHz clock. So your counter has to count from 0 to 1999 or from 1 
to 2000 (2000 Steps in total).

von Mubasheer A. (Company: Student) (muba)


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Okay thank you once again for the useful information given.

But yes I forgot to ask. Is this code is sythesisable cause finally I 
have to dump it to the board.

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