VHDL: counter checking

maestros wrote:
> use ieee.numeric_std.all;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
Never ever both together!
By ignoring this hint you will encounter some fairly strange errors due 
to multiple defined data types.

> I write the code but its not working, what is the problem? I am
> beginner in VHDL.
What do you expect? What does the code instead? How do you see that? 
What does your testbench look like?

> If the counter is counting then external signal is connected and if the
> counter is not counting then external signal is not connected.
A external signal is always connected in some way. Only its value 
changes. So do you mean "high" and "low" or '1' and '0'?

BTW:
The signal TEMP is only set once. Afterwards its never reset. That looks 
kind of strange...

BTW2:
Pls read the manual above each text box and use the [ vhdl ] tags for 
your code:

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Reply

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Rules — please read before posting

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    Post long source code as attachment, not in the text

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    :

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Formatting options

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    [vhdl]VHDL code[/vhdl]

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    :

maestros wrote:
> the CPLD input pin is pulled 'high' and when the external signal is
> connected the CPLD will get 3.9KHz square wave as input. I want to
> create a 'status' for external signal weather it is connected or not by
> giving high or low repectively on CPLD pin.
So the most easy way would be to check wether there is a change on the 
square-input now and then.

What I would do is nearly the same like you did:
Count up a counter with each system clock.
When the counter reaches a time of a little bit more than 1/(2*4kHz) = 
125µs = 125 system clock cycles  (lets assume here that the square 
signal is a perfect 50:50 square, otherwise it would be a rectangle and 
the time must be longer...) then there is no signal at the square input, 
so set "NoSignal" output is '1'.
Then check the square input for changes. When a change occures, reset 
the counter and additionally set the "NoSignal" output to '0'.

All in all it looks like this:

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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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use ieee.numeric_std.all;

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entity SYNC_det is

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Port (  CLK      : in  STD_LOGIC;

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        Square   : in  STD_LOGIC;

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        SquareDetected : out  STD_LOGIC := '0'

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                );

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end SYNC_det;

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architecture arch of SYNC_det is

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   signal sqsr : std_LOGIC_vector(1 downto 0) := "11"; -- shift register for edge detection, default value: external pullup

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   signal cnt : integer range 0 to 127 := 0;

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begin

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   counter_p: process(CLK) 

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   begin

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       if (rising_edge(CLK)) then

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            -- never ever use a async input without sync'ing it to the system clock!

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           sqsr <= sqsr(0)&Square;

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           -- check for edges 

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           if sqsr="10" or sqsr="01" then -- edge on SQUARE

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               cnt <= 0;

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               SquareDetected <= '1';

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           else                               

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               if cnt<127 then            -- count to highest value     

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                   cnt <= cnt + 1; 

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               else

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                   SquareDetected <= '0'; -- end of counter reached --> timeout, no more edges 

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               end if;

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           end if;

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       end if;

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   end process;

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end arch;

And the description above togehter with this testbench...

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LIBRARY ieee;

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USE ieee.std_logic_1164.ALL;

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ENTITY tb_sd IS

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END tb_sd;

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ARCHITECTURE behavior OF tb_sd IS 

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    COMPONENT SYNC_det

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    PORT(

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         CLK : IN  std_logic;

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         Square : IN  std_logic;

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         SquareDetected : OUT  std_logic

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        );

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    END COMPONENT;

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   signal CLK : std_logic := '0';

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   signal Square : std_logic := '1';

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   signal sq    :  std_logic := '1'; -- default value = 'high' due to pullup

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   signal sqen  :  std_logic := '1';

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   signal SquareDetected : std_logic;

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BEGIN

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   uut: SYNC_det PORT MAP (

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          CLK => CLK,

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          Square => Square,

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          SquareDetected => SquareDetected

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        );

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   clk  <= not clk after 500 ns;   -- 1MHz system clock

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   sq   <= not sq after 125 us;    -- 4kHz square wave 

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   sqen <= not sqen after 2250 us; -- enable for the square wave signal

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   Square <= sq and sqen;

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END;

... results in the waveform in the screenshot. Looks ok for me... ;-)

maestros wrote:
> Your code is perfectly  working, I have tested it on hardware also.
Nice to hear.
A hint: check out the symmetry of your square wave. When its changing a 
little bit from 50:50 to 48:52, then you will get short spikes on the 
SquareDetected output, because there is only a little margin on the 
counter (from 125 to 127). See WF_SD_DC48.PNG for that.
To get this waveform I changed the test bench a little to invoke the 
duty cycle in the 4kHz signal:

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   :

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   constant dc : real := 0.48;

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   :

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BEGIN

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   :

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   process begin

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      sq <= '1';

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      wait for dc * 250 us;

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      sq <= '0';

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      wait for (1.0-dc) * 250 us;

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   end process;

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   :

To be much more tolerant there it would be best to increase the top 
value of the counter to 255:

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   :

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   signal cnt : integer range 0 to 255 := 0;

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   :

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               if cnt<255 then            -- count to highest value

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   :

The reaction to detect a missing 4kHz square wave signal is then delayed 
by  129us. See WF_SD_DC48_cnt255.PNG at around 2.2ms.