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Forum: FPGA, VHDL & Verilog variable Component name


variable Component name
von arsalan ghasemian (Guest)

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Hello
I'm trying to use a component and part of my code is:
----------------------------------------------------------------
for i in 0 to n-1 loop
for o in 0 to n-1 loop
for p in 0 to n-1 loop
if (o-p = 32) then
bf(i): butterfly port map(s(o),s(p),w(0),g1(i);g1(i+1))
end if;
end loop;
end loop;
end loop;
-----------------------------------------------------------------
but I can't set the name of component "bf(i)" and I can't set a static 
name either, because it's going to make as much component as needed by 
defining n by user.
So my question is how can I do this.
Appreciate your help.
Best Regards.
Arsalan

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Re: variable Component name
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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I would expect the keyword "generate" somewhere...

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Re: variable Component name
von Vancouver (Guest)

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arsalan ghasemian wrote:
> but I can't set the name of component "bf(i)"

Why do you want to do this? During simulation/synthesis, each of your 
n^3 component instances will be assigned an individual name 
automatically. For example, something like bf_1_3_7, depending on the 
tools. So just write bf for the name. There is no need for indexing the 
instances in your code.

arsalan ghasemian wrote:
> as much component as needed by
> defining n by user

Of course you know, that n must be fixed. It can be set during compile 
time, but not later when the simulation is running or when the design is 
on an FPGA or ASIC.

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