Duke Scarring wrote:
> Yes. More simulation time (respectivly events) or more logged signals,
> both will increase the memory usage.
But, the simulator must do some paging and should not exceed the hard
limits regarding RAM usage, right? Slowing down due to paging I would
understand, but constantly increasing RAM usage until crash looks
definitely like a memory leak...
> First: 4GB and 32 bit should ring a bell. You're simply running out of
> address space.
> To track down memory leaks, I'd recommend valgrind under Linux and a
> cross check against the GHDL simulator, if it's VHDL.
Unfortunately, it is not purely VHDL, migrating everything to Linux
would be pretty difficult, since Vendor-dependent BFM infrastructure is
4GB & 32bit rings a bell! My question was whether it is a tool bug or
can someone create a memory leak at the testbench?
It occurs also with some other example designs, so it is likely that the
ModelSim Pro ME delivered within the Libero SoC 12.x has a bug.