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Forum: FPGA, VHDL & Verilog I2C inout port signal VHDL simulation


von Vahr (Guest)


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Hello there;

I have simulated a module with an external temperature sensor(LM75). In 
the top Level module the port were defined as "inout" type something 
like this
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      i2c_scl    : inout std_logic;
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      i2c_sda    : inout std_logic;
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      .;
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    achitecture behav of top_level is
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    Signal i2c_scl_int    : std_logic;
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    Signal i2c_sda_int    : std_logic;
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    . ;
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begin
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    i2c_scl <= '0' when i2c_scl_int ='0' else 'Z';
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    i2c_sda <= '0' when i2c_sda_int ='0' else 'Z';
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     ;
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end;

With the above Code my Output was "ZZ" every time and I have to modify 
the LM75 source Code as well as the i2c Controller Code to get a proper 
Output Signal.

I would like to know if there is any other Approach by not modifying the 
source Code and only add some Code in the testbench?

Thank you.

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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Vahr wrote:
> I would like to know if there is any other Approach by not modifying the
> source Code and only add some Code in the testbench?
Assign a weak "H" to the signals as you do it in real life with the I2C 
pullup resistors also.

: Edited by Moderator
von Vancouver (Guest)


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Vahr wrote:
> With the above Code my Output was "ZZ" every time

Independently from the i2c_scl_int and i2c_sda_int states?

von Vahr (Guest)


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Hello Lothar;

Thanks for your help. I do have a proper Output Signal now.

The Problem I am facing now is my i2c_sda Signal. It will start showing 
a proper waveform and later on just Change to "X" and some "H" and "0" 
and the waveform will get back to normal after some time.

Is there any way I can filter it to have a clean Signal?

many thanks

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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Vahr wrote:
> Is there any way I can filter it to have a clean Signal?
In real life you will have a proper signal.

To get rid of the 'X' in simulation you should initialise your signals 
in a way like that:
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    Signal i2c_scl_int    : std_logic := '1';
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    Signal i2c_sda_int    : std_logic := '1';

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