Ali wrote:
> p_debounce: process (s_1hzen, reset_i)
Congratulation: you formed a combinatorial loop.
1 | variable dbouncecntr : integer:=0;
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2 | begin
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3 | if reset_i = '1' then
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4 | :
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5 | else
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6 | :
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7 | dbouncecntr := dbouncecntr + 1; ---- here it is: a counter with no clock!
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I would write your REALLY BIG enable process somehow that way by using
integer as counters:
1 | p_slowen: process (clk_i, reset_i) -- can't see no need for the reset...
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2 | begin
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3 | if clk_i'event and clk_i = '1' then
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4 |
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5 | s_2khzen <= '0'; -- the default value is '0' but it
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6 | s_1hzen <= '0'; -- maybe overwritten furtherdown
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7 |
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8 | if s_enctr < COUNTVALUE then -- COUNTVALUE = (f_clk_i/2kHz)-1
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9 | s_enctr <= s_enctr + 1;
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10 | else
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11 | s_enctr <= 0;
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12 | s_2khzen <= '1'; -- 2kHz clock enable
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13 | if s_2khzcount<1999 then
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14 | s_2khzcount <= s_2khzcount+1;
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15 | else
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16 | s_1hzen <= '1'; -- 1Hz clock enable
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17 | end if;
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18 | end if;
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19 |
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20 | end if;
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21 | end process p_slowen;
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While editing I was heavily wondering, what the s_2khzen is for.
But I would use it for debouncing:
1 | p_debounce: process (clk_i, reset_i) -- USE OLNY ONE AND THE SAME CLOCK IN THE WHOLE DESIGN
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2 | -- again absolutely no need for the reset....
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3 | variable cntpb, cntsw : integer range 0 to 15 := 0;
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4 |
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5 | begin
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6 | if clk_i'event and clk_i = '1' then
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7 | if s_2khzen = '1' then
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8 | -- debounce sw
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9 | if swsync1 /= swdebounced then
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10 | cntsw<=0;
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11 | else
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12 | cntsw <= cntsw+1;
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13 | end if;
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14 | if cntsw = 15 then
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15 | swdebounced <= swsync1;
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16 | end if;
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17 |
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18 | --- same for pd
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19 |
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20 | end if;
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21 | end process;
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22 | swclean_o <= swdebounced;
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23 | pbclean_o <= pbdebounced;
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> You can also check the hole files that i upload for the vhdl folder.
I can't open rar files here. Why not simply attaching the VHDL flies
plus getting a bonus like sytax higlighting?
BTW: check the use of the vhdl tags...
1 | Rules — please read before posting
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2 | ...
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3 | Post long source code as attachment, not in the text
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4 |
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5 | Formatting options
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6 | ...
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7 | [vhdl]VHDL code[/vhdl]
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