Hello, I have to implement 8 bit ADC using PWM DAC. Master clock frequency of FPGA=100MHz, PWM frequency is 390khz. At 390khz, 48 dB has to be attenuated so the low pass filter frequency should be less than 1.563khz. 1)What is 48dB and why it has to be attenuated? 2)Why can’t I take low pass filter frequency as 390khz? A simple explanation would be helpful, Thank you!
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Arshi A. wrote: > 1)What is 48dB and why it has to be attenuated? 48dB is a factor by which the AC part of the PWM must be reduced at 390kHz. > 2)Why can’t I take low pass filter frequency as 390khz? When your low pass filter is designed for a cutoff frequency of 390kHz, then it has by definition a "attenuation" of -3dB at 390kHz. Because the -3dB frequency is the cutoff frequency. > so the low pass filter frequency should be less than 1.563khz. That means you have more than 2 decades distance between the PWM frequency and the 390kHz with the desired attenuation. Then its easy: just select such an order for your filter, that you get at least 48dB attenuation for little bit more decades. A first order filter like RC gives you 20dB/decade and 6bd/octave so it looks much alike a simple RC filter with a cutoff frequency of that 1,5kHz does the job.
Lothar M. wrote: > Arshi A. wrote: >> 1)What is 48dB and why it has to be attenuated? > 48dB is a factor by which the AC part of the PWM must be reduced at > 390kHz. Could you please explain what’s that AC part? Isn’t it SNR value for 8 bits?