Hi, I have a problem with Active HDL.
So I was given a 5 variable function with truth table.
I need to implement it on 4to1 mux and 2AND elements.
When I test only the mux it works perfectly, but when I combine it with
other mux and 2AND gate it doesn`t work..
Here is the code of mux:
And the mux`s combined code generated by Active HDL from my block
---- Signal declarations used on the diagram ----
Also I include screenshots of block diagram and waveform.
Thanks on advance for your help!
And sorry if question is stupid.
Yuriy B. wrote:> And the mux`s combined code generated by Active HDL
> use IEEE.std_logic_arith.all;> use IEEE.std_logic_signed.all;> use IEEE.std_logic_unsigned.all;
Using both the unsigned an signed math libs will bring the synthesizer
into trouble when encountering an arithmetic operation. Additionally in
that module neither of the three math libs is needed at all!
> but when I combine it with other mux and 2AND gate it doesn`t work..
What do you expect and what do you get instead? And how do you see that?
> Also I include screenshots of block diagram and waveform.
What can we see there? And what should be instead of that?
> Here is the code of mux:
Thats very bad coding style: because you don't have a default value for
F or an "else" assigning a value to F you will get a latch. A latch
alone is bad enough, but a accidently latch is much worse!
> f <= NET345 or NET336;
Think about the previous lament about latches and have a close look to
this OR gate.
And then try that:
And to get the "force-simulation-orgy" working complete the sensitivity
list of the process:
Because the sensitivity list MUST include every signal that may alter
the output/result of the process.
> When I test only the mux it works perfectly
Really? ... With that incomplete sensitivity list? ... Strange!
Just to twist the fingers a little i setup a testbench and simulated the
design with a complete (e,a,d) an the incomplete (e) sensitivity list
process(E,a,d)-- complete sensitivity list
F<='0';-- default value
Additionaly I added a screenshot with the correct senitivity list, but
no default value for f.
And for all of the screenshots I added the testbench. Its much easier
and protable(!!) than twiddling around with that force-thing in the
Yuriy B. wrote:> When I test only the mux it works perfectly
To finish up, I did a simulation of the mux itself also. I setup a
simple testbench for the 4-1 mux and simulated the original "perfectly
As I expected, this code does not do what it should due to the
incomplete sensitivity list. And the E input does not do what it should
do due to the missing default value.
With the correct code the mux works really perfectly... ;-)
Yuriy B. wrote:> Those lines aren`t working:
Can't see no problem there. Those are just signal assignments. Theres no
funcionality at all.
> Still the same problem
I took your code and my testbench and did therein some changes with
some letters and underlines and put them both together in the simulator
and found out: its working fine on Xilinx ISIM. I'm absolutely sure its
working on Aldec also, but my license ended, I must get a new one to
prove it ;-)
> when I remove those not needed libraries and hit compile they comeback,> don`t know why, compiler adds them by itself..
Its compiled out of that schematic. As a lucky guy I don't use any
graphic editor in any toolchain. And I don't use that signal forcing in
simulation either. Just plain VHDL from top to bottom. It can all I
need. Obviously that way I encounter less problems.
And thats what I urge you: forget those graphical interfaces, write the
testbench and the interconnect in VHDL.
Pls post screenshots as png files. They don't have any artifacts and are
A(0) => d,
A(1) => c,
A(2) => b,
A(3) => a,
Thats a really strange bit order. You get a knot in the brain twiddling