# Forum: FPGA, VHDL & Verilog Output undefined

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Hi, I have a problem with Active HDL.
So I was given a 5 variable function with truth table.
I need to implement it on 4to1 mux and 2AND elements.
When I test only the mux it works perfectly, but when I combine it with
other mux and 2AND gate it doesnt work..

Here is the code of mux:


 1 library IEEE;  2 use IEEE.STD_LOGIC_1164.all;  3 use IEEE.std_logic_unsigned.all;  4 entity mux_4_to_1 is  5  port(  6  E : in STD_LOGIC;  7  D : in STD_LOGIC_VECTOR(15 downto 0);  8  A : in STD_LOGIC_VECTOR(3 downto 0);  9  F : out STD_LOGIC  10  );  11 end mux_4_to_1;  12   13 architecture mux of mux_4_to_1 is  14 15 begin  16  process (E)  17  begin  18  if E = '1' then  19  F <= D(Conv_Integer(A));  20  end if;  21  end process;  22 end mux; 

And the muxs combined code generated by Active HDL from my block
diagram:

 1 library IEEE;  2 use IEEE.std_logic_1164.all;  3 use IEEE.std_logic_arith.all;  4 use IEEE.std_logic_signed.all;  5 use IEEE.std_logic_unsigned.all;  6 7 8 entity scheme is  9  port(  10  a : in STD_LOGIC;  11  b : in STD_LOGIC;  12  c : in STD_LOGIC;  13  d : in STD_LOGIC;  14  e : in STD_LOGIC;  15  Data : in STD_LOGIC_VECTOR(15 downto 0);  16  Data_1 : in STD_LOGIC_VECTOR(15 downto 0);  17  f : out STD_LOGIC  18  );  19 end scheme;  20 21 architecture scheme of scheme is  22   23 component mux_4_to_1  24  port (  25  A : in STD_LOGIC_VECTOR(3 downto 0);  26  D : in STD_LOGIC_VECTOR(15 downto 0);  27  E : in STD_LOGIC;  28  F : out STD_LOGIC  29  );  30 end component;  31 32 ---- Signal declarations used on the diagram ----  33 34 signal NET336 : STD_LOGIC;  35 signal NET345 : STD_LOGIC;  36 signal NET431 : STD_LOGIC;  37 38 begin  39   40 U1 : mux_4_to_1  41  port map(  42  A(0) => d,  43  A(1) => c,  44  A(2) => b,  45  A(3) => a,  46  D => Data,  47  E => NET431,  48  F => NET336  49  );  50 51 U2 : mux_4_to_1  52  port map(  53  A(0) => d,  54  A(1) => c,  55  A(2) => b,  56  A(3) => a,  57  D => Data_1,  58  E => e,  59  F => NET345  60  );  61 62 f <= NET345 or NET336;  63 64 NET431 <= not(e);  65 66 67 end scheme; 

Also I include screenshots of block diagram and waveform.
And sorry if question is stupid.

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Yuriy B. wrote:
> And the muxs combined code generated by Active HDL
Indeed? Strange...
> use IEEE.std_logic_arith.all;
> use IEEE.std_logic_signed.all;
> use IEEE.std_logic_unsigned.all;
Using both the unsigned an signed math libs will bring the synthesizer
into trouble when encountering an arithmetic operation. Additionally in
that module neither of the three math libs is needed at all!

> but when I combine it with other mux and 2AND gate it doesnt work..
What do you expect and what do you get instead? And how do you see that?

> Also I include screenshots of block diagram and waveform.
What can we see there? And what should be instead of that?

> Here is the code of mux:
 1  if E = '1' then  2  F <= D(Conv_Integer(A));  3  end if; 
Thats very bad coding style: because you don't have a default value for
F or an "else" assigning a value to F you will get a latch. A latch
alone is bad enough, but a accidently latch is much worse!

> f <= NET345 or NET336;
Think about the previous lament about latches and have a close look to
this OR gate.

And then try that:
 1  if E = '1' then  2  F <= D(Conv_Integer(A));  3  else  4  F <= '0';  5  end if; 
or that:
 1  F <= '0';  2  if E = '1' then  3  F <= D(Conv_Integer(A));  4  end if; 

And to get the "force-simulation-orgy" working complete the sensitivity
list of the process:
 1  process (E,A,D) 
Because the sensitivity list MUST include every signal that may alter
the output/result of the process.

> When I test only the mux it works perfectly
Really? ... With that incomplete sensitivity list? ... Strange!

: Edited by Moderator

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Just to twist the fingers a little i setup a testbench and simulated the
design with a complete (e,a,d) an the incomplete (e) sensitivity list
like that:
 1 :  2 :  3 begin  4  process (E,a,d) -- complete sensitivity list  5  begin  6  F <= '0'; -- default value  7  if E = '1' then  8  F <= D(Conv_Integer(A));  9  end if;  10 :  11 : 

no default value for f.

And for all of the screenshots I added the testbench. Its much easier
and protable(!!) than twiddling around with that force-thing in the
simulator.

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Yuriy B. wrote:
> When I test only the mux it works perfectly
To finish up, I did a simulation of the mux itself also. I setup a
simple testbench for the 4-1 mux and simulated the original "perfectly
working" code.
As I expected, this code does not do what it should due to the
incomplete sensitivity list. And the E input does not do what it should
do due to the missing default value.

With the correct code the mux works really perfectly...  ;-)

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I appericate Your reply!
But when I changed the mux code it still doesnt work..
Still the same problem

Heres the code of mux i corrected as You said:

 1 library IEEE;  2 use IEEE.STD_LOGIC_1164.all;  3 use IEEE.std_logic_unsigned.all;  4 entity mux_4_to_1 is  5  port(  6  E : in STD_LOGIC;  7  D : in STD_LOGIC_VECTOR(15 downto 0);  8  A : in STD_LOGIC_VECTOR(3 downto 0);  9  F : out STD_LOGIC  10  );  11 end mux_4_to_1;  12   13 architecture mux of mux_4_to_1 is  14 15 begin  16  process (E, A, D)  17  begin  18  F <= '0';  19  if E = '1' then  20  F <= D(Conv_Integer(A));  21  end if;  22  end process;  23 end mux; 

And the device code generated by active hdl, and by the way, when I
remove those not needed libraries and hit compile they comeback, dont
know why, compiler adds them by itself..

 1 library IEEE;  2 use IEEE.std_logic_1164.all;  3 use IEEE.std_logic_arith.all;  4 use IEEE.std_logic_signed.all;  5 use IEEE.std_logic_unsigned.all;  6 7 8 entity schm is  9  port(  10  a : in STD_LOGIC;  11  b : in STD_LOGIC;  12  c : in STD_LOGIC;  13  d : in STD_LOGIC;  14  e : in STD_LOGIC;  15  Data : in STD_LOGIC_VECTOR(15 downto 0);  16  Data1 : in STD_LOGIC_VECTOR(15 downto 0);  17  f : out STD_LOGIC  18  );  19 end schm;  20 21 architecture schm of schm is  22 23 ---- Component declarations -----  24 25 component mux_4_to_1  26  port (  27  A : in STD_LOGIC_VECTOR(3 downto 0);  28  D : in STD_LOGIC_VECTOR(15 downto 0);  29  E : in STD_LOGIC;  30  F : out STD_LOGIC  31  );  32 end component;  33 34 ---- Signal declarations used on the diagram ----  35 36 signal NET114 : STD_LOGIC;  37 signal NET124 : STD_LOGIC;  38 signal NET133 : STD_LOGIC;  39 40 begin  41 42 ---- Component instantiations ----  43 44 U2 : mux_4_to_1  45  port map(  46  A(0) => d,  47  A(1) => c,  48  A(2) => b,  49  A(3) => a,  50  D => Data,  51  E => NET114,  52  F => NET124  53  );  54 55 U3 : mux_4_to_1  56  port map(  57  A(0) => d,  58  A(1) => c,  59  A(2) => b,  60  A(3) => a,  61  D => Data1,  62  E => e,  63  F => NET133  64  );  65 66 NET114 <= not(e);  67 68 f <= NET133 or NET124;  69 70 71 end schm; 

Those lines arent working:

 1  F => NET133  2  --..--  3  F => NET124 

Thanks!

: Edited by User

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Yuriy B. wrote:
> Those lines arent working:
Can't see no problem there. Those are just signal assignments. Theres no
funcionality at all.

> Still the same problem
I took your code and my testbench and did therein some changes with
some letters and underlines and put them both together in the simulator
and found out: its working fine on Xilinx ISIM. I'm absolutely sure its
working on Aldec also, but my license ended, I must get a new one to
prove it  ;-)

> when I remove those not needed libraries and hit compile they comeback,
> dont know why, compiler adds them by itself..
Its compiled out of that schematic. As a lucky guy I don't use any
graphic editor in any toolchain. And I don't use that signal forcing in
simulation either. Just plain VHDL from top to bottom. It can all I
need. Obviously that way I encounter less problems.
And thats what I urge you: forget those graphical interfaces, write the
testbench and the interconnect in VHDL.

BTW:
> photo_2020-01-09_18-15-05.jpg
Pls post screenshots as png files. They don't have any artifacts and are
https://en.wikipedia.org/wiki/Compression_artifact

BTW2:
A(0) => d,
A(1) => c,
A(2) => b,
A(3) => a,
Thats a really strange bit order. You get a knot in the brain twiddling
it out.

: Edited by Moderator

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