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von Yuriy B. (wztch)


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Hi, I have a problem with Active HDL.
So I was given a 5 variable function with truth table.
I need to implement it on 4to1 mux and 2AND elements.
When I test only the mux it works perfectly, but when I combine it with 
other mux and 2AND gate it doesn`t work..

Here is the code of mux:

library IEEE;
use IEEE.STD_LOGIC_1164.all;  
use IEEE.std_logic_unsigned.all;

entity mux_4_to_1 is
   port(
     E : in STD_LOGIC;
     D : in STD_LOGIC_VECTOR(15 downto 0);
     A : in STD_LOGIC_VECTOR(3 downto 0);
     F : out STD_LOGIC
       );
end mux_4_to_1;
                         
architecture mux of mux_4_to_1 is    

begin  
  process (E)   
  begin
  if E = '1' then
  F <= D(Conv_Integer(A));        
  end if;    
  end process;
end mux;

And the mux`s combined code generated by Active HDL from my block 
diagram:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_unsigned.all;


entity scheme is
  port(
       a : in STD_LOGIC;
       b : in STD_LOGIC;
       c : in STD_LOGIC;
       d : in STD_LOGIC;
       e : in STD_LOGIC;
       Data : in STD_LOGIC_VECTOR(15 downto 0);
       Data_1 : in STD_LOGIC_VECTOR(15 downto 0);
       f : out STD_LOGIC
  );
end scheme;

architecture scheme of scheme is
                    
component mux_4_to_1
  port (
       A : in STD_LOGIC_VECTOR(3 downto 0);
       D : in STD_LOGIC_VECTOR(15 downto 0);
       E : in STD_LOGIC;
       F : out STD_LOGIC
  );
end component;

---- Signal declarations used on the diagram ----

signal NET336 : STD_LOGIC;
signal NET345 : STD_LOGIC;
signal NET431 : STD_LOGIC;

begin
                    
U1 : mux_4_to_1
  port map(
       A(0) => d,
       A(1) => c,
       A(2) => b,
       A(3) => a,
       D => Data,
       E => NET431,
       F => NET336
  );

U2 : mux_4_to_1
  port map(
       A(0) => d,
       A(1) => c,
       A(2) => b,
       A(3) => a,
       D => Data_1,
       E => e,
       F => NET345
  );

f <= NET345 or NET336;

NET431 <= not(e);


end scheme;

Also I include screenshots of block diagram and waveform.
Thanks on advance for your help!
And sorry if question is stupid.

von Lothar M. (lkmiller) (Moderator)


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Yuriy B. wrote:
> And the mux`s combined code generated by Active HDL
Indeed? Strange...
> use IEEE.std_logic_arith.all;
> use IEEE.std_logic_signed.all;
> use IEEE.std_logic_unsigned.all;
Using both the unsigned an signed math libs will bring the synthesizer 
into trouble when encountering an arithmetic operation. Additionally in 
that module neither of the three math libs is needed at all!

> but when I combine it with other mux and 2AND gate it doesn`t work..
What do you expect and what do you get instead? And how do you see that?

> Also I include screenshots of block diagram and waveform.
What can we see there? And what should be instead of that?

> Here is the code of mux:
  if E = '1' then
     F <= D(Conv_Integer(A));        
  end if;
Thats very bad coding style: because you don't have a default value for 
F or an "else" assigning a value to F you will get a latch. A latch 
alone is bad enough, but a accidently latch is much worse!

> f <= NET345 or NET336;
Think about the previous lament about latches and have a close look to 
this OR gate.

And then try that:
  if E = '1' then
     F <= D(Conv_Integer(A));        
  else
     F <= '0';
  end if;
or that:
  F <= '0';
  if E = '1' then
     F <= D(Conv_Integer(A));        
  end if;

And to get the "force-simulation-orgy" working complete the sensitivity 
list of the process:
  process (E,A,D)
Because the sensitivity list MUST include every signal that may alter 
the output/result of the process.

> When I test only the mux it works perfectly
Really? ... With that incomplete sensitivity list? ... Strange!

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


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Just to twist the fingers a little i setup a testbench and simulated the 
design with a complete (e,a,d) an the incomplete (e) sensitivity list 
like that:
:
:
begin  
  process (E,a,d) -- complete sensitivity list
  begin
    F <= '0';   -- default value
    if E = '1' then
      F <= D(Conv_Integer(A));        
    end if;  
:
:

Additionaly I added a screenshot with the correct senitivity list, but 
no default value for f.

And for all of the screenshots I added the testbench. Its much easier 
and protable(!!) than twiddling around with that force-thing in the 
simulator.

von Lothar M. (lkmiller) (Moderator)


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Yuriy B. wrote:
> When I test only the mux it works perfectly
To finish up, I did a simulation of the mux itself also. I setup a 
simple testbench for the 4-1 mux and simulated the original "perfectly 
working" code.
As I expected, this code does not do what it should due to the 
incomplete sensitivity list. And the E input does not do what it should 
do due to the missing default value.

With the correct code the mux works really perfectly...  ;-)

von Yuriy B. (wztch)


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I appericate Your reply!
But when I changed the mux code it still doesn`t work..
Still the same problem

Here`s the code of mux i corrected as You said:
library IEEE;
use IEEE.STD_LOGIC_1164.all;  
use IEEE.std_logic_unsigned.all;

entity mux_4_to_1 is
   port(
     E : in STD_LOGIC;
     D : in STD_LOGIC_VECTOR(15 downto 0);
     A : in STD_LOGIC_VECTOR(3 downto 0);
     F : out STD_LOGIC
       );
end mux_4_to_1;
                         
architecture mux of mux_4_to_1 is    

begin  
  process (E, A, D)   
  begin    
  F <= '0';
  if E = '1' then
      F <= D(Conv_Integer(A));
  end if;    
  end process;
end mux;

And the device code generated by active hdl, and by the way, when I 
remove those not needed libraries and hit compile they comeback, don`t 
know why, compiler adds them by itself..
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_unsigned.all;


entity schm is
  port(
       a : in STD_LOGIC;
       b : in STD_LOGIC;
       c : in STD_LOGIC;
       d : in STD_LOGIC;
       e : in STD_LOGIC;
       Data : in STD_LOGIC_VECTOR(15 downto 0);
       Data1 : in STD_LOGIC_VECTOR(15 downto 0);
       f : out STD_LOGIC
  );
end schm;

architecture schm of schm is

---- Component declarations -----

component mux_4_to_1
  port (
       A : in STD_LOGIC_VECTOR(3 downto 0);
       D : in STD_LOGIC_VECTOR(15 downto 0);
       E : in STD_LOGIC;
       F : out STD_LOGIC
  );
end component;

---- Signal declarations used on the diagram ----

signal NET114 : STD_LOGIC;
signal NET124 : STD_LOGIC;
signal NET133 : STD_LOGIC;

begin

----  Component instantiations  ----

U2 : mux_4_to_1
  port map(
       A(0) => d,
       A(1) => c,
       A(2) => b,
       A(3) => a,
       D => Data,
       E => NET114,
       F => NET124
  );

U3 : mux_4_to_1
  port map(
       A(0) => d,
       A(1) => c,
       A(2) => b,
       A(3) => a,
       D => Data1,
       E => e,
       F => NET133
  );

NET114 <= not(e);

f <= NET133 or NET124;


end schm;

Those lines aren`t working:
       F => NET133
       --..--
       F => NET124

Thanks!

: Edited by User
von Lothar M. (lkmiller) (Moderator)


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Yuriy B. wrote:
> Those lines aren`t working:
Can't see no problem there. Those are just signal assignments. Theres no 
funcionality at all.

> Still the same problem
I took your code and my testbench and did therein some changes with 
some letters and underlines and put them both together in the simulator 
and found out: its working fine on Xilinx ISIM. I'm absolutely sure its 
working on Aldec also, but my license ended, I must get a new one to 
prove it  ;-)

> when I remove those not needed libraries and hit compile they comeback,
> don`t know why, compiler adds them by itself..
Its compiled out of that schematic. As a lucky guy I don't use any 
graphic editor in any toolchain. And I don't use that signal forcing in 
simulation either. Just plain VHDL from top to bottom. It can all I 
need. Obviously that way I encounter less problems.
And thats what I urge you: forget those graphical interfaces, write the 
testbench and the interconnect in VHDL.

BTW:
> photo_2020-01-09_18-15-05.jpg
Pls post screenshots as png files. They don't have any artifacts and are 
clearly readable.
https://en.wikipedia.org/wiki/Compression_artifact

BTW2:
       A(0) => d,
       A(1) => c,
       A(2) => b,
       A(3) => a,
Thats a really strange bit order. You get a knot in the brain twiddling 
it out.

: Edited by Moderator

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