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Forum: FPGA, VHDL & Verilog assign clock as signal


von pall (Guest)


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hi...
 I am writing a code where i have to generate sclk for ADC .here
  sys clock frequency and SCLK frequency of ADC are same .pl tell how to 
assign clock as a signal under if a condition for eg

process(Clk)

begin
....
.....

  if (counter > 4 and counter < 15) then
            S_clk<= Clk;




Thanks

von Lothar M. (lkmiller) (Moderator)


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pall wrote:
> sys clock frequency and SCLK frequency of ADC are same
Is the sysclock that slow or the SCLK that high?
What frequencies do you have?

von pall (Guest)


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my system clock frequency is 50Mhz and same frequency i have to generate 
for SCLK of ADC .i attempted to assign SCLK same as my system clock but 
its not working

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