Forum: FPGA, VHDL & Verilog High signal for two clock cicles

von Francesco T. (fransisco94)

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Good morning, I'm tring to write a code able to raise up the output 
signal (called Input_err_ASCII) to '1' logic level. I tried using a 
Counter, but it doesn't work very well.

Follow a part of my code :

My_clk_counter : Counter
    generic map (Nbit => Nbit)
    port map (
      input => "00000001",
      clk => clk,
      resetn => Counter_ON,
      output => cicli_clk

Counter_ON <= '1' when (unsigned(Msg_in)<97 or unsigned(cicli_clk)>2);
Input_err_ASCII <= '1' when (unsigned(Msg_in)<97 and 
unsigned(cicli_clk)<2) else '0';

Counter_on : is a signal able to activate the Counter
Cicli_clk : is the counter's output

I need your help, please.

von Vancouver (Guest)

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Francesco T. wrote:
> but it doesn't work very well.

Well, this is a little bit unspecific, isn't it?
What did you expect from your design, and how does it behave instead? 
Did you do any simulation, and what is the result? Did you check if the 
counter works correctly?
With the information you provided it is impossible to help you. This may 
be the reason why nobody is answering your question.

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