Good morning, I'm tring to write a code able to raise up the output
signal (called Input_err_ASCII) to '1' logic level. I tried using a
Counter, but it doesn't work very well.
Follow a part of my code :
My_clk_counter : Counter
generic map (Nbit => Nbit)
port map (
input => "00000001",
clk => clk,
resetn => Counter_ON,
output => cicli_clk
);
Counter_ON <= '1' when (unsigned(Msg_in)<97 or unsigned(cicli_clk)>2);
Input_err_ASCII <= '1' when (unsigned(Msg_in)<97 and
unsigned(cicli_clk)<2) else '0';
Counter_on : is a signal able to activate the Counter
Cicli_clk : is the counter's output
I need your help, please.