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Forum: FPGA, VHDL & Verilog More actuals found than formals in port map ERROR


von Ömer Kenan U. (Company: Student) (omerkenan)


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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Fullsubtractor is
    Port ( X : in  STD_LOGIC;
           Y : in  STD_LOGIC;
           Z : in  STD_LOGIC;
           D : out  STD_LOGIC;
           B : out  STD_LOGIC);
end Fullsubtractor;

architecture Behavioral of Fullsubtractor is
signal t: STD_LOGIC_VECTOR(7 downto 0);

Component ThreeToEightDecoder
Port( X,Y,Z: IN STD_LOGIC;
      D: OUT STD_LOGIC_VECTOR(7 downto 0));
End Component;

begin

Stage1 : ThreeToEightDecoder Port 
Map(X,Y,Z,t(0),t(1),t(2),t(3),t(4),t(5),t(6),t(7));
D<=(t(4) or t(2) or t(1) or t(7));
B<=(t(3) or t(5) or t(2));

end Behavioral;


I have "More actuals found than formals in port map" error and I can't 
realize why.

von Lothar M. (lkmiller) (Moderator)


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Ömer Kenan U. wrote:
> I have "More actuals found than formals in port map" error and I can't
> realize why.
The component ThreeToEightDecoder has 4 ports (3 input ports 1 bit 
wide, and 1 output port 8 bits wide).
You try to connnect 11 1-bit signals to those 4 ports. A slight 
mismatch.

This would match:
Stage1 : ThreeToEightDecoder Port Map(X,Y,Z,t);

I suggest to use explicit assignment, then such simple things won't 
happen any more.
Stage1 : ThreeToEightDecoder Port Map(X>X,Y->,Z-Z,D->t);

BTW:
What do you want to do with this strange bit order in the wrong port 
list: t(0),t(1),t(2),t(3),t(4),t(5),t(6),t(7)?
Do you want to flip bits 0->7, 1->6,..., 7->0?

: Edited by Moderator
von Ömer Kenan U. (Company: Student) (omerkenan)


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Isn't this:

Stage1 : ThreeToEightDecoder Port 
Map(X,Y,Z,t(0),t(1),t(2),t(3),t(4),t(5),t(6),t(7));

mean;
 (input0,input1,input2,output1,output2,output3,output4,output5,output6,ou 
tput7,output8);

von Ömer Kenan U. (Company: Student) (omerkenan)


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I solved my problem.Thanks for help.Correct code as this:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Fullsubtractor is
    Port ( X : in  STD_LOGIC;
           Y : in  STD_LOGIC;
           Z : in  STD_LOGIC;
           D : out  STD_LOGIC;
           B : out  STD_LOGIC);
end Fullsubtractor;

architecture Behavioral of Fullsubtractor is
signal t: STD_LOGIC_VECTOR(7 downto 0);

Component ThreeToEightDecoder
    Port( X: IN STD_LOGIC;
         Y: IN STD_LOGIC;
       Z: IN STD_LOGIC;
          D: OUT STD_LOGIC_VECTOR(7 downto 0));
End Component;

begin

Stage1 : ThreeToEightDecoder Port Map(X,Y,Z,t(7 downto 0));
D<=(t(4) or t(2) or t(1) or t(7));
B<=(t(3) or t(5) or t(2));

end Behavioral;

von Lothar M. (lkmiller) (Moderator)


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Ömer Kenan U. wrote:
> (7 downto 0)
As already said. that's not necessary because both vectors are declared 
with the same width. This would be enough :... Port Map(X,Y,Z,t);

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