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Forum: FPGA, VHDL & Verilog Using a BFM in system verilog code


von Dip K. (Guest)


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Hi all,
I am new to system Verilog and learning to write a test bench for 
already existing code.
I have a master.sv file which has the code for SPI master. I have 
written a basic testbench
(master_tb.sv)to test the master, but to simulate the SPI bus I wanted 
to use a verification IP already provided by sysWip(http://syswip.com).
The VIP has an interface file and a package file.
How do I use it in my code?
where do I instantiate the interface, start the spi environment and the 
connection?
do I need to change anything in my master.sv file?

my master.sv file is given below
module master
  (
    input clk,
    output sdi,
    input sdo,
    output sclk,
    output [2:0] slave_select
  );

i have just typed the code for the test bench.

module master_tb();
wire sclk;
reg clk;
reg sdo;
wire sdi;
wire [2:0] slave_select;

master_tb dut(
     .sclk(sclk),
     .sdo(sdo),
.......
and so on

where do i do the import of the interface?
do i need master interface too? or just the slave interfcae is needed to 
test my code?
Is there any simple sample code availbale?

von Vancouver (Guest)


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Dip K. wrote:
> where do i do the import of the interface?

You should look into the example testbench provided with the VIP, 
everything is shown there. First, try to simulate their example.

> do i need master interface too? or just the slave interfcae is needed to
> test my code?

That depends on the type of your own SPI controller model: Is it a 
master or a slave?

> Is there any simple sample code availbale?

You did not spend so much time in reading the documentation, did you? 
There is an examples folder which contains the sample code you are 
searching for.

However, you should yourself make familiar with the concepts of 
interfaces and class based verification, these are some of the most 
important and advanced concepts in SystemVerilog.

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