I am new to system Verilog and learning to write a test bench for
already existing code.
I have a master.sv file which has the code for SPI master. I have
written a basic testbench
(master_tb.sv)to test the master, but to simulate the SPI bus I wanted
to use a verification IP already provided by sysWip(http://syswip.com).
The VIP has an interface file and a package file.
How do I use it in my code?
where do I instantiate the interface, start the spi environment and the
do I need to change anything in my master.sv file?
my master.sv file is given below
output [2:0] slave_select
i have just typed the code for the test bench.
wire [2:0] slave_select;
and so on
where do i do the import of the interface?
do i need master interface too? or just the slave interfcae is needed to
test my code?
Is there any simple sample code availbale?